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PDF BU7988KVT Data sheet ( Hoja de datos )
| Número de pieza | BU7988KVT | |
| Descripción | 56bit LVDS Transmitter 56:8 Serializer | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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LVDS Interface ICs
56bit LVDS Transmitter
56:8 Serializer
BU7988KVT
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and
number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number
by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
■Wide dot clock range : Single(112MHz)/Dual(224MHz)(NTSC, VGA, SVGA, WXGA UXGA)
■Support spread spectrum clock generator.
■Clock edge selectable.
■Support reduced swing LVDS for low EMI.
■Power down mode.
■Package TQFP100V
●Applications
Flat Plane Display
●Precaution
■This chip is not designed to protect from radioactivity.
Jun. 2008
1 page  
●Pin Description
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Table 1 : Pin Description
Pin Name
Pin No.
Type
Descriptions
TA1P, TA1N
TB1P, TB1N
TC1P, TC1N
TD1P, TD1N
TCLK1P, TCLK1N
TA2P, TA2N
TB2P, TB2N
TC2P TC2N
TD2P, TD2N
TCLK2P, TCLK2N
R17～R10
G17～G10
B17～B10
R27～R20
G27～G20
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
29, 30
60, 59, 58, 57, 54, 53, 52, 51
68, 67, 66, 65, 64, 63, 62, 61
78, 77, 76, 75, 74, 73, 70, 69
86, 85, 84, 83, 82, 81, 80, 79
96, 95, 94, 93, 92, 91, 90, 89
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
IN
IN
IN
IN
IN
LVDS data out
LVDS clock out
LVDS data out
LVDS clock out
1ｓｔ Pixel data input.
2ｓｔ Pixel data inputs.
B27～B20
6, 5, 2, 1, 100, 99, 98, 97
IN
DE 9 IN DATA-ENABLE input.
VSYNC
8 IN VSYNC input.
HSYNC
7 IN HSYNC input.
CLKIN
MAP
XRST
FLIP
10 IN Clock Input.
14
IN
LVDS mapping table select.
See Table11-14 and Figure11-14.
19
IN
H : Normal operation,
L : Power down (all outputs are Hi-Z)
21 IN LVDS output pin select. See Table10.
5 / 27
5 Page 
■AC characteristics
Table 8 : Switching Characteristics （VDD=3.3V, Ta=25℃）
Symbol
Parameter
Min
tTCIT
CLK IN Transition time
-
Dual In /Dual Out
8.9
Dual In / Single Out
17.8
tTCP
CLK IN Period
Single In / Dual Out
6.7
Single In / Single Out
8.9
tTCH CLK IN High Time 0.35tTCP
tTCL CLK IN Low Time 0.35tTCP
Dual In /Dual Out
tTCD
CLK IN to
TCLK+/-Delay
Single In/Single Out
Dual In / Single Out
-
-
Single In / Dual Out
-
tTS CMOS Data Setup to CLK IN
2.5
tTH CMOS Data Hold from CLK IN
0
Dual In /Dual Out
8.9
tTCOP
CLK OUT Period
Dual In / Single Out
Single In / Dual Out
8.9
13.3
Single In / Single Out
8.9
tLVT
tTOP1
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
Tck12
tTPLL
LVDS Transition Time
Output Data Position 0
Output Data Position 1
Output Data Position 2
Output Data Position 3
Output Data Position 4
Output Data Position 5
Output Data Position 6
Skew Time between
TCLKXP and TCLKYP
Phase Lock Loop Set Time
-
-0.2
tTCP -0.2
7
2 tTCP -0.2
7
3 tTCP -0.2
7
4 tTCP -0.2
7
5 tTCP -0.2
7
6 tTCP -0.2
7
-
-
Typ
-
-
-
-
0.5tTCP
0.5tTCP
TBD
TBD
TBD
-
-
-
-
-
0.6
0.0
tTCP
7
2 tTCP
7
3 tTCP
7
4 tTCP
7
5 tTCP
7
6 tTCP
7
-
-
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Max
5.0
125.0
62.5
250.0
125.0
0.65tTCP
0.65tTCP
-
-
-
-
-
125.0
125.0
125.0
125.0
1.5
+0.2
tTCP +0.2
7
2 tTCP +0.2
7
3 tTCP +0.2
7
4 tTCP +0.2
7
5 tTCP +0.2
7
6 tTCP +0.2
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5 ns
10.0 ms
11 / 27
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| PDF Descargar | [ Datasheet BU7988KVT.PDF ] | |
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