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PDF 68HC05BD2 Data sheet ( Hoja de datos )
| Número de pieza | 68HC05BD2 | |
| Descripción | SPECIFICATION REV 2.0 (General Release) | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor, Inc.
HC05BD7GRS/H
www.RDaEtaSVhee2t4.U0.com
68HC05BD7
68HC705BD7
68HC05BD2
SPECIFICATION
REV 2.0
(General Release)
© January 20, 1998
Technical Operation Taiwan
Taipei, Taiwan
For More Information On This Product,
Go to: www.freescale.com
1 page  
MC68HC05BD7 RevF. 2r.e0escale SemicondGuEcNtoERr,AILnRcE.LEASE SPECIFICATION
9.3.6
9.4
9.5
www.DataSheet4U.com
DDC Data Receive Register (DDRR)..................................44
Data Sequence .........................................................................45
Program Algorithm....................................................................45
SECTION 10 SYNC PROCESSOR...................................................... 49
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
Introduction ...............................................................................49
Functional Blocks......................................................................49
Polarity Detection ................................................................49
Sync Signal Counters..........................................................49
Polarity Controlled HSYNO/VSYNO Outputs ......................49
CLAMP Pulse Output ..........................................................50
Registers................................................................................... 51
Sync Processor Control and Status Register (SPCSR) ......51
Sync Processor Input/Output Control Register (SPIOCR) ..52
Vertical Frequency Registers (VFRs)..................................53
Hsync Frequency Registers (HFRs)....................................54
System Operation .....................................................................54
SECTION 11 MULTI-FUNCTION TIMER............................................. 57
11.1
11.2
11.2.1
11.2.2
Introduction ...............................................................................57
Register ....................................................................................57
Multi-function Timer Control/status Register .......................57
MFT Timer Counter Register...............................................59
SECTION 12 A/D CONVERTER.......................................................... 61
12.1
12.2
12.2.1
12.3
12.3.1
12.3.2
12.4
Introduction ...............................................................................61
Input .......................................................................................... 61
ADC0-ADC3 ........................................................................61
Registers................................................................................... 62
ADC Control/status Register ...............................................62
ADC Channel Register ........................................................62
Program Example .....................................................................63
SECTION 13 ELECTRICAL SPECIFICATIONS.................................. 65
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
13.6
Maximum Ratings .....................................................................65
Thermal Characteristics............................................................65
DC Electrical Characteristics ....................................................66
Control Timing ..........................................................................67
DDC12AB TIMING....................................................................68
DDC12AB Interface Input Signal Timing .............................68
DDC12AB Interface Output Signal Timing ..........................68
HSYNC/VSYNC Input Timing ...................................................69
SECTION 14
14.1
14.2
14.3
MECHANICAL SPECIFICATIONS ................................ 71
Introduction ...............................................................................71
40-Pin DIP Package (Case 711-03) .........................................71
42-Pin SDIP Package (Case 858-01) .......................................71
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5 Page 
MC68HC05BD7 RevF. 2r.e0escale SemicondGuEcNtoERr,AILnRcE.LEASE SPECIFICATION
www.DataSheet4U.com
SECTION 1
GENERAL DESCRIPTION
The MC68HC05BD7 HCMOS microcontroller is a member of the M68HC05 Family of low-
cost single-chip microcontrollers. It is particularly suitable as multi-sync computer monitor
controller. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM,
ROM, DDC12AB module, parallel I/O, Pulse Width Modulator, Multi-Function Timer, 6-bit
ADC, and SYNC Processor.
1.1 Features
1.1.1
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Hardware Features
HC05 Core
Low cost, HCMOS technology
40-pin DIP and 42-pin SDIP packages
256 Bytes of RAM for HC05BD2
384 Bytes of RAM for HC05BD7HC705BD7
5.75K-Bytes of User ROM for HC05BD2
11.75K-Bytes of User ROM for HC05BD7
11.5K-Bytes of User EPROM for HC705BD7
26 Bidirectional I/O lines: 14 dedicated and 12 multiplexed I/O lines. 4 of
the 14 dedicated I/O lines and 6 of the 12 multiplexed I/O lines have max.
+12V or +5V open-drain output buffers
16 x 8-bit PWM channels: Two 8-bit PWM channels have +12V open-
drain outputs: 8 dedicated 8-bit PWM channels have +5V open-drain
output options
6-bit ADC with 4 selectable input channels
Multi-Function Timer (MFT) with Periodic Interrupt
Sync Signal Processor module for processing horizontal, vertical,
composite, and SOG SYNC signals; frequency counting; polarity
detection; polarity controlled HSYNO and VSYNO or extracted VSYNC
outputs, and CLAMP pulse output
DDC12AB† module contains DDC1 hardware and multi-master I2C††
hardware for DDC2AB protocol
Software maskable Edge-Sensitive or Edge and Level-Sensitive External
Interrupt
†DDC is a standard defined by VESA.
††I2C-bus is a proprietary Philips interface bus.
SECTION 1: GENERAL DESCRIPTION
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 68HC05BD2.PDF ] | |
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