PDF MC14LC5002 Data sheet ( Hoja de datos )

Número de pieza	MC14LC5002
Descripción	72-Segment / 128-Segment LCD Drivers
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA 72-Segment / 128-Segment LCD Drivers CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv- ers.The MC14LC5002 is the same as MC14LC5003 except for 72 segments. The three devices are functionally the same except for their data input pro- tocols. The MC14LC5002/5003 use a serial interface data input protocol. The devices may be interfaced to the MC68HCXX product families using a minimal amount of software (see example).The MC14LC5004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowl- edge bit back to the transmitter after each eight-bit byte is received. MC14LC5004 also has a “read mode”, whereby data sent to the device may be retrieved via the IIC bus. The MC14LC5002/5003/5004 drive the liquid crystal displays in a multi- plexed-by-four conﬁguration. The devices accept data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the ﬂexibility of formatting the segment data externally. Devices are independently addressable via a two-wire (or three-wire) com- munication link which can be common with other peripheral devices. The MC14LC5003/5004 are low cost version of MC145003 and MC145004 without cascading function. • Drives 72 Segments Per MC14LC5002’s Package • Drives 128 Segments Per MC14LC5003/5004’s Package • May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom • Quiescent Supply Current: 30 µA @ 2.7 V VDD • Operating Voltage Range: 2.7 to 5.5 V • Operating Temperature Range: - 40 to 85°C • Separate Access to LCD Drive Section’s Supply Voltage to Allow for Tem- perature Compensation • See Application Notes AN1066 and AN442 www.DataSheet4U.com MC14LC5002 MC14LC5003 MC14LC5004 QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A ORDERING INFORMATION MC14LC5002FB TQFP MC14LC5003FU QFP MC14LC5004FU QFP MCC14LC5003 BARE DIE MCC14LC5004 BARE DIE MCC14LC5003Z AU BUMP DIE MCC14LC5004Z AU BUMP DIE REV 7 02/98 MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–3 1 page ELECTRICAL CHARACTERISTICS (Continued) Characteristic Symbol VDD V VLCD V Min Typical Max www.DataSheet4U.com Unit Frequencies OSC2 Frequency @ R1; R1 = 200 kΩ fOSC2 5 5 100 — 150 kHz BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 kΩ fBP fOSC2 5 5 5 5 100 23 — — 150 Hz 33 kHz Average DC Offset Voltage (BP Relative to FP) VOO 5 2.8 -50 — +50 mV Input Voltage “0” Level VIL 2.8 5 — — 0.85 V VIL 5.5 5 — — 1.65 “1” Level VIH VIH 2.8 5 5.5 5 2 3.85 — — — — Output Drive Current — Backplanes VO = 2.65 V VO = 0.15 V VO = 1.08V VO = 1.72 V VO = 5.35 V VO = 0.15 V VO = 1.98 V IBH * IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL 5 2.8 -240 5 2.8 -240 5 2.8 260 5 2.8 260 5 2.8 40 5 2.8 — 5 2.8 -40 5 2.8 — 5 5.5 -520 5 5.5 -520 5 5.5 600 5 5.5 600 5 5.5 55 5 5.5 — — — — — — — — — — — — — — — — µA — — — — 2 — -1 — — — — — 1 VO = 3.52 V IBH 5 5.5 -35 — — IBL 5 5.5 — — -1 Pulse Width, Data Clock (Figure 1) tw 5 3 100 — 100 — — ns — DCLK Rise/Fall Time (Figure 1) tr, tf 5 3 — — 120 µs — — 120 Setup Time, Din to DCLK (Figure 2) tsu 5 3 20 — — ns 20 — — Hold Time, Din to DCLK (Figure 2) th 5 3 40 — — ns 60 — — Hold Time for START condition (Figure 2) tstart 5 3 100 — 100 — — ns — Hold Time for STOP condition (Figure 2) tstop 5 3 100 — 100 — — ns — DCLK Low to ENB High (Figure 3) th 5 3 20 — — ns 20 — — ENB High to DCLK High (Figure 3) trec 5 3 20 — — ns 20 — — ENB High Pulse Width (Figure 3) tw 5 3 100 — 100 — — ns — ENB Low to DCLK High (Figure 3) tsu 5 3 20 — — ns 20 — — NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change. MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–7 5 Page FP1 FP2 FP32 DIN BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 DCLK START ENB (IF USED) 8-BITS ADDRESS 128-BITS DATA STOP ENABLE PULSE MAY OCCUR AS REQUIRED BUT MUST BE DURING DCLK HIGH. Figure 7a. Data Input—MC14LC5002/5003 11 Page

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