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AGL600 데이터시트 PDF




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부품번호 AGL600 기능
기능 (AGLxxx) IGLOO Low-Power Flash FPGAs
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AGL600 데이터시트, 핀배열, 회로
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
www.DataSheet4U.com
v1.3
®
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
High Capacity
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM®-enabled IGLOO®
devices) via JTAG (IEEE 1532–compliant)1
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
IGLOO Product Family
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and
LVCMOS 2.5 V / 5.0 V Input1
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate1 and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL1
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1SRkAbMitsoafnFdlasFhIFROOsMwUithserVaNroianbvloe-laAtsipleecMt-eRmatoiory4,608-Bit1 RAM
Blocks (×1, ×2, ×4, ×9,
True Dual-Port SRAM
a(enxdce×p1t8×o1r8g)a1nizations)
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
IGLOO Devices
AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000
ARM-Enabled IGLOO Devices
M1AGL250 M1AGL400 M1AGL600 M1AGL1000
System Gates
15 k
30 k
60 k 125 k 250 k
400 k
600 k
1M
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
128
384
5
256 512 1,024 2,048 –
768
1,536 3,072
6,144
9,216
13,824
24,576
5
10 16
24
32
36
53
18 36
36
54 108
144
4,608-Bit Blocks
48
8
12 24
32
FlashROM Bits
Secure (AES) ISP 1
Integrated PLL in CCCs 2
VersaNet Globals 3
I/O Banks
Maximum User I/Os
1k
1k
1k 1k
1k
1k
1k
1k
Yes Yes
Yes
Yes
Yes
Yes
11
1
1
1
1
6
6
18 18
18
18
18
18
2
2
22
4
4
4
4
49
81
96 133 143 194 235
300
Package Pins
UC/CS
QFN
VQFP
FBGA
QN68
UC81/CS81
QN48, QN68,
QN132
VQ100
CS121
QN132
VQ100
FG144 5
CS196
QN132
VQ100
FG144
CS196 4
QN132 4,5
VQ100
FG144
CS196
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
Notes:
1. AES is not available for ARM-enabled IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
4. The M1AGL250 device does not support this package.
5. Device/package support TBD
6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze
Technology handbook.
1 AGL015 and AGL030 devices do not support this feature.
‡ Supported only by AGL015 and AGL030 devices.
December 2008
© 2008 Actel Corporation
I




AGL600 pdf, 반도체, 판매, 대치품
IGLOO Low-Power Flash FPGAs
www.DataSheet4U.com
Temperature Grade Offerings
Package
AGL015
AGL030
AGL060
AGL125
AGL250
AGL400 AGL600 AGL1000
M1AGL250 4 M1AGL400 M1AGL600 M1AGL1000
QN48
– C, I –
––
QN68
C, I –
––
UC81
– C, I –
––
CS81
– C, I –
––
CS121
– C, I –
––
VQ100
QN132
– C, I C, I C, I C, I – –
C, I C, I 3 C, I C, I 3
CS196
FG144
– C, I C, I C, I –
C, I 3
C, I
C, I
C, I C, I C, I
FG256
– – – – – C, I C, I C, I
CS281
– – – – – – C, I C, I
FG484
– – – – – C, I C, I C, I
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
3. Device/package support TBD.
4. The M1AGL250 device does not support FG256 or QN132 packages.
Speed Grade and Temperature Grade Matrix
Temperature Grade
C2
I3
–F 1 Std.
✓✓
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in
the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
IV v1.3

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AGL600 전자부품, 판매, 대치품
IGLOO Low-PowewrwFwla.DsahtaFSPheGetA4Us .com
external memory components; instead it retains all necessary information to resume operation
immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device
architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO
family a cost-effective ASIC replacement solution, especially for applications in the consumer,
networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-
based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot
be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error
detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic
utilization without compromising device routability or performance. Logic functions within the
device are interconnected through a four-level routing hierarchy.
IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The
IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on
page 1-4 and Figure 1-2 on page 1-4):
• Flash*Freeze technology
• FPGA VersaTiles
• Dedicated FlashROM
• Dedicated SRAM/FIFO memory
• Extensive CCCs and PLLs
• Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup
table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.
The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture
flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
† The AGL015 and AGL030 do not support PLL or SRAM.
v1.3
1-3

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AGL600

(AGLxxx) IGLOO Low-Power Flash FPGAs

Actel Corporation
Actel Corporation

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