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Número de pieza | W9812G2GH | |
Descripción | a high-speed synchronous dynamic random access memory (SDRAM) | |
Fabricantes | Winbond | |
Logotipo | ||
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W9812G2GH
Table of Contents-
1 GENERAL DESCRIPTION .............................................................................................................. 3
2 FEATURES...................................................................................................................................... 3
3 AVAILABLE PART NUMBER .......................................................................................................... 3
4 PIN CONFIGURATION.................................................................................................................... 4
5 PIN DESCRIPTION ......................................................................................................................... 5
6 BLOCK DIAGRAM........................................................................................................................... 6
7 FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1 Power Up and Initialization.................................................................................................... 7
7.2 Programming Mode Register ................................................................................................ 7
7.3 Bank Activate Command ....................................................................................................... 7
7.4 Read and Write Access Modes ............................................................................................. 7
7.5 Burst Read Command ........................................................................................................... 8
7.6 Burst Write Command ........................................................................................................... 8
7.7 Read Interrupted by a Read .................................................................................................. 8
7.8 Read Interrupted by a Write .................................................................................................. 8
7.9 Write Interrupted by a Write .................................................................................................. 8
7.10 Write Interrupted by a Read .................................................................................................. 8
7.11 Burst Stop Command ............................................................................................................ 9
7.12 Addressing Sequence of Sequential Mode ........................................................................... 9
7.13 Addressing Sequence of Interleave Mode ............................................................................ 9
7.14 Auto-precharge Command .................................................................................................. 10
7.15 Precharge Command .......................................................................................................... 10
7.16 Self Refresh Command ....................................................................................................... 10
7.17 Power Down Mode .............................................................................................................. 11
7.18 No Operation Command...................................................................................................... 11
7.19 Deselect Command ............................................................................................................. 11
7.20 Clock Suspend Mode .......................................................................................................... 11
8 OPERATION MODE...................................................................................................................... 12
9 ELECTRICAL CHARACTERISTICS ............................................................................................. 13
9.1 Absolute Maximum Ratings................................................................................................. 13
9.2 Recommended DC Operating Conditions ........................................................................... 13
9.3 Capacitance......................................................................................................................... 13
9.4 DC Characteristics............................................................................................................... 14
Publication Release Date: Aug. 13,2007
- 1 - Revision A07
1 page www.DataSheet4U.com
W9812G2GH
5 PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
25-27, 60-66, 24,21 A0−A11
Address
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
22,23
BS0, BS1 Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2,4,5,7,8,10,11,13,74,
76,77,79,80,82,83,85,
31,33,34,36,37,39,40,
42,45,47,48,50,51,53,
54,56
DQ0−DQ31
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
20 CS Chip Select decoder is disabled, new command is ignored and
previous operation continues.
19
RAS
Row
Strobe
Address
Command input. When sampled
clock, RAS , CAS and WE
at the
define
rising edge of
the operation
the
to be
executed.
18
CAS
Column
Address Strobe
Referred to
RAS
17
16,71,28,59
WE
DQM0~3
68 CLK
67 CKE
1,15,29,43
44,58,72,86
VDD
VSS
3,9,35,41,49,55,75,81 VDDQ
6,12,32,38,46,52,78,
84
14,30,57,69,70,73
VSSQ
NC
Write Enable Referred to RAS
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O buffer immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection
Publication Release Date: Aug. 13,2007
- 5 - Revision A07
5 Page www.DataSheet4U.com
W9812G2GH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don’t cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
- 11 -
Publication Release Date: Aug. 13,2007
Revision A07
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet W9812G2GH.PDF ] |
Número de pieza | Descripción | Fabricantes |
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