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78P2352 데이터시트 PDF




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부품번호 78P2352 기능
기능 Dual Channel OC-3/ STM1-E/ E4 LIU
제조업체 TDK Semiconductor
로고 TDK Semiconductor 로고


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78P2352 데이터시트, 핀배열, 회로
DESCRIPTION
The 78P2352 is TDK’s second generation LIU for
155 Mbit/s SDH/SONET (OC-3, STS-3, or STM-1)
and 140Mbit/s PDH (E4) applications. The device is
a dual channel, single chip solution that includes an
integrated CDR in the transmit path for flexible NRZ
to CMI conversion. The device can interface to 75
coaxial cable using CMI coding or directly to a fiber
optics module using NRZ coding. The 78P2352 is
compliant with all respective ANSI, ITU-T, and
Telcordia standards for jitter tolerance, generation,
and transfer.
APPLICATIONS
Central Office Interconnects
DSLAMs
Add Drop Multiplexers (ADMs)
PDH/SDH test equipment
BLOCK DIAGRAM
78P2352www.DataSheet4U.com
Dual Channel
OC-3/ STM1-E/ E4 LIU
TARGET DATASHEET
MARCH 2003
FEATURES
G.703 compliant line interface for 139.264 Mbps
or 155.52 Mbps CMI-coded coax transmission.
LVPECL compatible line interface for 155.52
Mbps NRZ-coded fiber applications.
Integrated adaptive CMI equalizer and CDR in
receive path.
Serial, LVPECL-compatible system interface
with integrated CDR in transmit path for NRZ to
CMI conversion.
4-bit parallel CMOS system interface with
master/slave Tx clock modes.
Configurable via HW control pins or 4-wire µP
interface
Operates from a single reference clock input.
Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
Provides Loss of Lock (LOL), CMI Line Code
Violation (LCV), and G.775 compliant Loss of
Signal (LOS) detection.
Receiver Monitor Mode
Operates from a single 3.3V supply
128-pin TQFP (JEDEC LQFP) package
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
Lock Detect
Tx CDR
FIFO
EACH CHANNEL: Tx
CMI
Encoder
CMI
Decoder
CMI-LCV
Detect
Rx CDR
Lock Detect
EACH CHANNEL: Rx
Adaptive
Eq.
G.775
LOS
Detect
TXxCKP/N
CMIxP/N
ECLxP/N
RXxP/N
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78P2352 pdf, 반도체, 판매, 대치품
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
www.DataSheet4U.com
FUNCTIONAL DESCRIPTION
The 78P2352 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbit/s and 155.52Mbit/s signals and the
digital universe.
The chip is controllable through pins or serial port
register settings. In hardware mode (pin control) the
SPSL pin must be low. In software mode (SPSL pin
high), control pins are disabled and the 78P2352
must be configured via the 4-wire serial port.
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device operates in according to the table
below. This control combined with CKSL also
selects the global reference frequency.
Rate
E4
STM-1, STS-3, OC-3
SDO_E4 pin
High
Low
E4 bit
1
0
The SEN_CMI pin or CMI register bit selects one of
two media for reception and transmission: coaxial
cable in CMI mode or optical fiber in ECL (NRZ)
mode. Independent operation is available with
register controls (CMI bit).
Media (coding)
75 ohm Coax (CMI)
Fiber (NRZ)
SEN_CMI pin
High
Low
CMI bit
1
0
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be four bit parallel or serial.
For each interface there are different clocking
schemes for the transmitter. These modes and
their controls are described in the TRANSMITTER
OPERATION section.
REFERENCE CLOCK
The 78P2352 requires a reference clock supplied to
the CKREFP/N pins. For reference frequencies of
77.76MHz or lower, the device accepts a single
ended CMOS input at CKREFP. For reference
frequencies of 139.264/155.52MHz, the device
accepts a differential clock input at CKREFP/N. The
frequency of this reference input is selected by the
rate selection and the CKSL control pin or register
bit.
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference Frequency
SDO_E4 low SDO_E4 high
19.44MHz
77.76MHz
155.52MHz
17.408MHz
N/A
139.264MHz
E4 bit = 0
19.44MHz
77.76MHz
155.52MHz
E4 bit = 1
17.408MHz
N/A
139.264MHz
RECEIVER OPERATION
The receiver accepts serial data, at 155.52Mbit/s or
139.264Mbit/s from the RXxP/N inputs. In CMI
mode, the CMI-coded inputs come from a coaxial
cable that is transformer-coupled to the chip. In ECL
(NRZ) mode, the input pins receive NRZ LVPECL
level signals from an O/E converter.
The CMI signal first enters an AGC, which has a
selectable gain range setting. When Receiver
Monitor Mode is enabled, the AGC can compensate
for a monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer designed to overcome inter-symbol
interference caused by long cable. The variable
gain differential amplifier automatically controls the
gain to maintain a constant voltage level output
regardless of the input voltage level. In ECL (NRZ)
mode, the input signals bypass the adaptive
equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which uses a
reference frequency derived from the clock applied
to the CKREFP/N pins.
After the clock and data have been recovered, the
data is converted to binary by the CMI to binary
decoder. The CMI Line Code Violation (LCV)
detector will flag code errors while the decoder
continues to function normally. The three conditions
that will flag a LCV are:
‘0’ has a falling transition mid-bit instead of a
rising transition
A high ‘1’ is recovered when it should have
been a low ‘1’
A low ‘1’ is recovered when it should have
been a high ‘1’
In serial mode, the clock and data are transmitted
through the LVPECL drivers. In parallel mode, the
data is converted into four bit parallel segments
before being transmitted through the CMOS drivers.
Receiver Monitor Mode
The SCK_MON pin or MONx register bit puts the
receiver in monitor mode and adds 20dB of flat gain
to the receive signal before equalization. The
SCK_MON pin controls the monitor mode for both
channels simultaneously. Individual monitor mode
selection can be done using the MONx register bit.
Note that Receiver Monitor Mode is available in CMI
mode only.
Loss of Signal / Loss of Lock
The 78P2352 includes standards compliant Loss of
Signal (LOS) and Loss of Lock (LOL) indicators for
the receive signals. During LOS conditions, the
receive data outputs are squelched while the receive
clock outputs a line rate clock generated from the
reference clock input. The LOS indicator is intended
for electrical CMI interfaces only.
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78P2352 전자부품, 판매, 대치품
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
www.DataSheet4U.com
LOOPBACK MODES
SERIAL CONTROL INTERFACE
In SW mode, LLBKx and RLBKx bits are provided to
activate the local and remote loopback modes
respectively. In HW mode, the LPBKx pins can be
used to activate local and remote loopback modes
as shown below.
LPBK pin
Low
Float
High
Loopback Mode
Normal operation
Remote (digital) Loopback:
Recovered receive clock and data
looped back to transmitter
Local (analog) Loopback:
Transmit clock and data looped back to
receiver
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
Lock Detect
Tx CDR
FIFO
EACH CHANNEL: Tx
CMI
Encoder
CMI
Decoder
CMI-LCV
Detect
Rx CDR
Lock Detect
EACH CHANNEL: Rx
Adaptive
Eq.
G.775
LOS
Detect
TXxCKP/N
CMIxP/N
ECLxP/N
RXxP/N
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
Figure 6: Local (Analog) Loopback
Lock Detect
Tx CDR
FIFO
EACH CHANNEL: Tx
CMI
Encoder
TXxCKP/N
CMIxP/N
ECLxP/N
CMI
Decoder
CMI-LCV
Detect
Rx CDR
Lock Detect
EACH CHANNEL: Rx
Adaptive
Eq.
G.775
LOS
Detect
RXxP/N
The serial port controlled register allows a generic
controller to interface with the 78P2352. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
trimming. The SPSL pin must be high in order to
use the serial port.
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations. It can also be used to select a particular
device allowing SCK_MON, SDI_PAR and SDO_E4
to be bussed together. SCK_MON is the clock input
that times the data on SDI_PAR and SDO_E4. Data
on SDI_PAR is latched in on the rising-edge of
SCK_MON, and data on SDO_E4 is clocked out
using the falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB) first.
The mode and address bit assignment and register
table are shown in the following section.
SDO_E4 is a tristate capable output. It is used to
output register data during a read operation.
SDO_E4 output is normally high impedance, and is
enabled only during the duration when register data
is being clocked out. Read data is clocked out least
significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tristate capable, SDI_PAR and SDO_E4 can be
connected together to simplify connections.
The maximum clock frequency for register access is
20MHz.
PROGRAMMABLE INTERRUPTS
Figure 7: Remote (Digital) Loopback
POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Upon initial power-up, a reset pulse is internally
generated. This resets all registers to their default
values as well as all state machines within the
transceiver to known initial values. The reset signal
is also brought out to the POR pin. The POR pin is
a special function pin that allows for the following:
In addition to the receiver LOS and LOL status pins,
the 78P2352 provides a programmable interrupt for
each transmitter and receiver. In HW control mode,
the default functions of each interrupt is as follows:
INTTXx = Transmit Loss of Lock (TXLOL) or
FIFO error (FERR)
INTRXx = CMI Line Code Violation
(CMIERR)
Override the internal POR signal by driving in
an external POR signal;
Use the POR signal to drive other IC’s power-
on reset;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
The internal resistance of the POR pin is
approximately 5k.
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