Datasheet.kr   

78P2351R 데이터시트 PDF




Teridian Semiconductor에서 제조한 전자 부품 78P2351R은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 78P2351R 자료 제공

부품번호 78P2351R 기능
기능 Serial 155M NRZ to CMI Converter
제조업체 Teridian Semiconductor
로고 Teridian Semiconductor 로고


78P2351R 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 31 페이지수

미리보기를 사용할 수 없습니다

78P2351R 데이터시트, 핀배열, 회로
DESCRIPTION
The 78P2351R is Teridian’s second generation Line
Interface Unit (LIU) for 155 Mbit/s electrical SDH
interfaces (STM1e). The device is a single chip
solution that includes an integrated Clock & Data
Recovery in both the transmit and receive paths for
easy, cost efficient NRZ to CMI conversion.
The device interfaces to 75coaxial cable through
wideband transformers and can handle over 12.7dB
of cable loss. By eliminating the needs for
synchronous clocks, the small 78P2351R (7x7mm
MLF package) is ideal for new STM1e (ES1) Small
Form-factor Pluggable (SFP) transceiver modules.
APPLICATIONS
STM1e SFP modules
SDH/ATM Line Cards
Add Drop Multiplexers (ADMs)
PDH/SDH Test Equipment
Digital Microwave Radios
Multi-Service Switches
78P2351Rwww.DataSheet4U.com
Serial 155M
NRZ to CMI Converter
DATA SHEET
AUGUST 2006
FEATURES
ITU-T G.703 compliant, adjustable cable driver
for 155.52 Mbps CMI-coded coax transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 12.7dB of cable loss
LVPECL-compatible system interface with
integrated CDR in transmit path for flexible NRZ
to CMI conversion
Configurable via HW control pins or 4-wire serial
port interface
Compliant with ANSI T1.105.03-1994; ITU-T
G.813, G.825, G.958; and Telcordia GR-253-
CORE for jitter performance
Receive Loss of Signal (Rx LOS) detection
Receive Monitor Mode handles up to 20dB of
flat loss (at max 6dB cable loss)
Optional fixed backplane equalizer compensates
for up to 1.5m of trace
Operates from a single 3.3V supply
Available in a small 7x7mm 56-pin QFN
package
Industrial Temperature: -40˚C to +85˚C
BLOCK DIAGRAM
75ohm Coax
(CMI Encoded)
78P2351R
Adaptive
Eq.
CDR
CDR
Fixed
Eq.
CMI
ENDEC
Tx Disable
TD +
TD -
RD +
RD -
LVPECL Data
(NRZ Encoded)
Rx LOS
Page: 1 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1




78P2351R pdf, 반도체, 판매, 대치품
FUNCTIONAL DESCRIPTION
The 78P2351R contains all the necessary transmit
and receive circuitry for connection between
155.52Mbit/s NRZ data sources (STS-3/STM-1) and
CMI encoded electrical interfaces (ES1/STM-1e).
The 78P2351R system interface mimics a 3.3V
optical transceiver module and only requires a
reference clock and wideband transformer to
complete the electrical interface. The chip can be
controlled via control pins or serial port register
settings.
In hardware mode (pin control) the SPSL pin must
be low. Additionally, the following unused pins
must be set accordingly:
SDO pin must be tied low
SDI pin must be tied low
SEN pin must be tied high
In software mode (SPSL pin high), control pins set
register defaults upon power-up or reset. The
78P2351R can then be configured via the 4-wire
serial control interface. See Pin Descriptions
section for more information.
REFERENCE CLOCK
The 78P2351R requires a reference clock supplied
to the CKREFP/N pins. For reference frequencies of
19.44MHz or 77.76MHz, the device accepts a single
ended CMOS level input at CKREFP (with CKREFN
pin tied to ground). For reference frequency of
155.52MHz, the device accepts a differential
LVPECL clock input at CKREFP/N. The frequency
of this reference input is selected by either the CKSL
control pin or register bit as follows:
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference
Frequency
19.44MHz
77.76MHz
155.52MHz
RECEIVER OPERATION
The receiver accepts an ITU-T G.703 compliant CMI
encoded signal at 155.52Mbit/s from the RXP/N
inputs. When properly terminated and transformer-
coupled to the line, the receiver can handle over
12.7dB of cable loss. The receiver’s jitter tolerance
exceeds all relevant standards even with 12.7dB
worth of cable attenuation and inter-symbol
interference (ISI). See Receiver Jitter Tolerance
section for more info.
www7.D8atPaS2he3et54U1.cRom
Serial 155M
NRZ to CMI Converter
The recovered CMI signal first enters an AGC and
an adaptive equalizer designed to overcome inter-
symbol interference caused by long cable lengths.
The variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
utilizes a line-rate reference frequency derived from
the clock applied to the CKREFP/N pins. After the
clock and data have been recovered, the data is
decoded to binary by the CMI decoder. The
SODP/N pins output the recovered NRZ data at
LVPECL levels.
Receiver Monitor Mode
The SCK_MON pin or MON register bit puts the
receiver in monitor mode and adds approximately
20dB of flat gain to the receive signal before
equalization. Rx Monitor Mode can handle 20dB of
flat loss typical of monitoring points with up to 6dB
(typical 225ft) of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Receive Loss of Signal Detect
The 78P2351R includes a Loss of Signal (LOS)
detector. When the peak value of the received
signal is less than approximately 19dB below
nominal for approximately 110 UI, Receive Loss of
Signal is asserted. The Rx LOS signal is cleared
when the received signal is greater than
approximately 18dB below nominal for 110 UI.
During Rx LOS conditions, the receive clock will
remain on the last phase tap of the Rx DLL
outputting a stable clock while the receive data
outputs are squelched and held at logic ‘0’.
Note: Rx Loss of Signal detection is disabled
during Local Loopback and Receive Monitor
Modes.
Page: 4 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1

4페이지










78P2351R 전자부품, 판매, 대치품
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50 µs after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function
analog pin that allows for the following:
Override the internal POR signal by driving in
an external active low reset signal;
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
www7.D8atPaS2he3et54U1.cRom
Serial 155M
NRZ to CMI Converter
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2351R. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
The serial interface consists of 4 pins:
Serial Port Enable (SEN),
Serial Clock (SCK_MON),
Serial Data In (SDI),
Serial Data Out (SDO).
The SEN pin initiates the read and write operations.
It can also be used to select a particular device
allowing SCK_MON, SDI and SDO to be bussed
together.
SCK_MON is the clock input that times the data on
SDI and SDO. Data on SDI is latched in on the
rising-edge of SCK_MON, and data on SDO is
clocked out using the falling edge of SCK_MON.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only during
the duration when register data is being clocked out.
Read data is clocked out least significant bit (LSB)
first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
Page: 7 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1

7페이지


구       성 총 31 페이지수
다운로드[ 78P2351R.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
78P2351

Single Channel OC-3/ STM1-E/ E4 LIU

TDK Semiconductor
TDK Semiconductor
78P2351R

Serial 155M NRZ to CMI Converter

Teridian Semiconductor
Teridian Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵