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PDF 73M1903C Data sheet ( Hoja de datos )
| Número de pieza | 73M1903C | |
| Descripción | Modem Analog Front End | |
| Fabricantes | Teridian Semiconductor | |
| Logotipo |  |
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Simplifying System IntegrationTM
DS_1903C_033
DESCRIPTION
The 73M1903C Analog Front End (AFE) IC includes
fully differential hybrid driver outputs, which connect to
the telephone line interface through a transformer-
based DAA. The receive pins are also fully differential
for maximum flexibility and performance. This
arrangement allows for the design of a high
performance hybrid circuit to improve signal to noise
performance under low receive level conditions, and
compatibility with any standard transformer intended
for PSTN communications applications.
The device incorporates a programmable sample rate
circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
16.0 kHz by programming the pre-scaler NCO and the
PLL NCO.
The 73M1903C device incorporates a digital host
interface that is compatible with the serial ports found
on most commercially available DSPs and processors
and exchanges both payload and control information
with the host. This interface can be configured as a
single master/slave mode or as a daisy chain mode
that allows the user to connect up to eight 73M1903C
devices to a single host for multi Analog Front End
applications, such as, central server modems.
Costs saving features of the device include an input
reference frequency circuit, which accepts a range of
crystals from 4.9-27 MHz. It also accepts external
reference clock values between 1 MHz and 40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of materials
(BOM).
The 73M1903C also supports two analog loop back
and one digital loop back test modes.
73M1903Cwww.DataSheet4U.com
Modem Analog Front End
DATA SHEET
March 2010
FEATURES
• Two pairs of software selectable transmit
differential outputs for worldwide impedance
driver implementations.
• Up to 56 kbps (V.92) performance
• Programmable sample rates (7.2-16.0 kHz)
• Reference clock range of 1-40 MHz
• Crystal frequency range of 4.9-27 MHz
• Master or slave mode operation
• Daisy chain configurable synchronous serial
Host interface
• Low power modes
• Fully differential receiver and transmitter
Drivers for transformer interface
• 3.0 V – 3.6 V operation
• 5 V tolerant I/O
• Industrial temperature range (-40 to +85 °C)
• JATE compliant transmit spectrum
• Package option: 32-pin QFN
APPLICATIONS
• Central site server modems
• Set Top Boxes
• Personal Video Recorders (PVR)
• Multifunction Peripherals (MFP)
• Fax Machines
• Internet Appliances
• Game Consoles
• Point of Sale Terminals
• Automatic Teller Machines
• Speaker Phones
• Digital Answering Machines
• RF Modems
TXAP1
TXAN1
TXAP2
TXAN2
RXAP
RXAN
(HYBRID)
Transmit
Drivers/
Filters
Analog
Sigma
Delta
VBG
Ref.
Receiver
MUX/
Filters
DAC
Control
Registers
Serial
Port
GPIO
HOOK
DAA
controls
Clock
Control
Logic
SCLK
SDIN
SDOUT
FS
FSD
Crystal
Rev. 5.0
1
1 page  
DS_1903C_033
Pin Name
RXAN
RXAP
TXAN1
TXAN2
TXAP1
TXAP2
Type
I
I
O
O
O
O
Pin #
14
15
10
11
12
13
SCLK
I/O 8
SDOUT
SDIN
FS
TYPE
O 32
I 29
O7
I 27
SckMode
I 28
FSD
O 21
73M1903CwwDwa.DtaataSShheeete4Ut .com
Description
Receive analog negative input.
Receive analog positive input.
Transmit analog negative output 1.
Transmit analog negative output 2.
Transmit analog positive output 1.
Transmit analog positive output 2.
Serial interface clock. With master mode and SCLK
continuous selected, Freq = 256*Fs ( =2.4576 MHz for
Fs=9.6 kHz). For slave mode, this pin must be pulled
down by a resistor (<4.7 kΩ).
Serial data output (or input to the host).
Serial data input (or output from the host).
Frame synchronization. (Active Low)
Type of frame sync. 0 = late (mode0); 1 = early (mode1).
Weak-pulled high – default
Controls the SCLK behavior after FS. Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle.
Delayed frame sync to support daisy chain mode with
additional 73M1903C devices.
Rev. 5.0
5
5 Page 
DS_1903C_033
73M1903CwwDwa.DtaataSShheeete4Ut .com
Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of
the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the
1/4 of the data frame sync interval. In all cases involving slave and daisy chain operation, only hardware
controlled Control Frames are supported. Software requested control frames are not allowed.
In slave mode the relationship of Fs and Fsclk is Fsclk/Fs, with a range of from 96 to 256 SCLKs per Fs.
Again, the host controls the relationship of FS to SCLK, with the condition that Fsclk>750 kHz and
Fsys=4608*Fs. The 79M1903C PLL must be programmed to generate Fsys with those conditions. To
program the 73M1903C NCOs, OSCIN (Fsclk)=SCLK=Fref when Pdvsr=1 and Prst=0 in the calculations.
Fsys in the previous discussion is Fvco in the calculations which is equal to 4608*Fs. For example, two
typical cases are Fsclk=256*Fs and Fsclk=144*Fs.
For the case when Fsclk=256*Fs and Fs=8 kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864 MHz, and Sclk=256*8 kHz=2.048 MHz. Therefore Ndvsr=36.864/2.048=18 (12h)
and Nrst=0
For the case when Fsclk=144*Fs and d Fs=8 kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864 MHz and Sclk=144*8 kHz=1.152 MHz. Therefore Ndvsr=36.864/1.152=32 (20h)
and Nrst=0
Rev. 5.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 73M1903C.PDF ] | |
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