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PDF 78Q8430 Data sheet ( Hoja de datos )
| Número de pieza | 78Q8430 | |
| Descripción | 10/100 Ethernet MAC and PHY | |
| Fabricantes | Teridian Semiconductor | |
| Logotipo |  |
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78Q8430 10/100 Ethernet
MAC and PHY
Simplifying System Integration TM
DATA SHEET
DESCRIPTION
The Teridian 78Q8430 is a 10/100 Fast Ethernet
controller supporting multi-media offload. The
device is optimized for host processor offloading
and throughput enhancements for demanding
multi-media applications found in Set Top Box,
IP Video and Broadband Media Appliance
applications. The 78Q8430 seamlessly
interfaces to non-PCI processors through a
simplified pseudo SRAM-like Host Bus Interface
supporting 32/16/8 bit data bus widths.
Supported features include IEEE802.3x flow
control and full IEEE802.3 and 802.3u standards
compliance.
Supporting 10Base-T and 100Base-TX, the
transceiver provides Auto MDI-X cable
cross-over correction, AUTO Negotiation, Link
Configuration and full/half duplex support with
full duplex flow control. The line interface
requires only a dual 1:1 isolation transformer.
Numerous packet processing and IP address
resolution control functions are incorporated,
including an extensive set of Error Monitoring,
Reporting and Troubleshooting features. The
78Q8430 provides optimal 10/100 Ethernet
connectivity in demanding video streaming and
mixed-media applications.
BENEFITS
• Support for IEEE-802.3, IEEE-802.3u and
IEEE-802.3-2000 Annex 31.B
• Low host CPU utilization/overhead with
minimal software driver overhead and small
driver memory space requirements
• Improved packet processing, low latency and
low host CPU utilization
• Highest performance streaming Video over IP
• Optimized performance in mixed media
application such as video, data and voice
• Ease of use, faster development cycles, high
throughput
• Optimized power conservation with automatic
turn on when needed
• Reduced host CPU utilization and overhead
• Improved packet processing
• Optimized performance in mixed media
applications
March 2009
FEATURES
• Single chip 10Base-T/100Base-TX
IEEE-802.3 compliant MAC and PHY
Adaptive 32 kB SRAM FIFO memory
allocation between Tx and Rx paths
Queue independent user settable water
marks
Per queue status indication
• Address Resolution Controller (ARC)
Multiple perfect address filtering: 8 default
(max 12)
Wildcard address filtering, individual,
multicast and broadcast address
recognition and filtering
Positive/negative filtering and promiscuous
mode
• 64 kB JUMBO packet support
• QoS: 4 Transmit priority levels
• Non-PCI pseudo-SRAM Host Bus Interface
8-bit, 16-bit and 32-bit bus width
Big/little endian support for 16-bit/32-bit bus
widths
Asynchronous (100 MHz) and synchronous
(50 MHz) bus clock support
• Low power and flexible power supply
management
Power down/save
Wake on LAN (Magic Packet™, OnNow
packet)
Link status change
• Traffic Offload Engine Functionality
Transfer frame: APF & ICMP Echo
IP Firewall configuration: drop frames on
source IP address
IP Checksum
• Available in an industrial temperature range
(-40 °C to +85 °C)
• RoHS compliant (6/6) lead-free package
APPLICATIONS
• Satellite, cable and IPTV Set Top Boxes
• Multi Media Residential Gateways
• High Definition 1080p/1080i DTVs
• IP-PVR and video distribution systems
• Digital Video Recorders/Players
• Routers and IADs
• Video over IP system, IP-PBX
• IP Security Cameras / PVRs
• Low latency industrial automation
Rev. 1.2
© 2009 Teridian Semiconductor Corporation
1
1 page  
DS_8430_001
78Q843w0wDwa.DtaataSShheeete4Ut .com
12 Package Mechanical Drawing (100-pin LQFP) ............................................................................... 86
13 Ordering Information ........................................................................................................................ 87
14 Related Documentation.................................................................................................................... 87
15 Contact Information.......................................................................................................................... 87
Tables
Table 1: Pin Legend .................................................................................................................................... 12
Table 2: Clock Pin Descriptions .................................................................................................................. 12
Table 3: MDI Pin Descriptions..................................................................................................................... 13
Table 4: LED Pin Descriptions .................................................................................................................... 13
Table 5: EEPROM Interface Pin Descriptions ............................................................................................ 13
Table 6: GBI Data Pin Descriptions ............................................................................................................ 14
Table 7: GBI Address Pin Descriptions....................................................................................................... 15
Table 8: GBI Control Pin Descriptions ........................................................................................................ 15
Table 9: Chip Mode Pin Descriptions.......................................................................................................... 16
Table 10: JTAG Pin Descriptions ................................................................................................................ 16
Table 11: Power Pin Descriptions............................................................................................................... 17
Table 12: Absolute Maximum Ratings ........................................................................................................ 18
Table 13: Recommended Operating Conditions......................................................................................... 18
Table 14: DC Characteristics ...................................................................................................................... 18
Table 15: Digital I/O Characteristics ........................................................................................................... 19
Table 16: MII 100Base-TX Transmit Timing ............................................................................................... 19
Table 17: MII 100Base-TX Transmitter (Informative) ................................................................................. 19
Table 18: MII 100Base-TX Receiver Timing ............................................................................................... 20
Table 19: MII 10Base-T Transmitter Timing ............................................................................................... 20
Table 20: MII 10Base-T Transmitter (Informative) ...................................................................................... 20
Table 21: MII 10Base-T Receive Timing..................................................................................................... 21
Table 22: Transmit Data Buffer Example.................................................................................................... 28
Table 23: Counter Summary ....................................................................................................................... 30
Table 24: CAM Rules Associated with Unicast Filter Bytes........................................................................ 34
Table 25: CAM Rules Associated with Multicast Filter Bytes ..................................................................... 36
Table 26: Control Logic Actions .................................................................................................................. 38
Table 27: RCR Match Control ..................................................................................................................... 39
Table 28: Ethernet Frame for Classification................................................................................................ 39
Table 29: Process Destination Address Rules............................................................................................ 40
Table 30: Process Source Address Rules .................................................................................................. 42
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules................. 42
Table 32: Process Rules for OnNow Packet............................................................................................... 43
Table 33: Process Rules for Magic Packet ................................................................................................. 43
Table 34: PHY Register Group ................................................................................................................... 74
Table 35: Isolation Transformers ................................................................................................................ 83
Table 36: Reference Crystal ....................................................................................................................... 83
Table 37: 78Q8430 Order Numbers and Packaging Marks........................................................................ 87
Rev. 1.2
5
5 Page 
DS_8430_001
2 Pinout
The 78Q8430 is available in a 14x14 mm 100-pin LQFP package.
78Q843w0wDwa.DtaataSShheeete4Ut .com
BOOTSZ0
GND
TMS
TDI
TRST
TCLK
RESET
VCC
ADDR1
ADDR0
WR
OE
MEMWAIT
GND
BUSCLK
CS
VCC
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
78Q8430
Figure 7: Pinout
75 PROMCS
74 PROMCLK
73 PME
72 INT
71 VCC
70 GND
69 DATA31
68 DATA30
67 DATA29
66 DATA28
65 DATA27
64 DATA26
63 DATA25
62 DATA24
61 VCC
60 GND
59 DATA23
58 DATA22
57 DATA21
56 DATA20
55 DATA19
54 DATA18
53 DATA17
52 DATA16
51 VCC
Rev. 1.2
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 78Q8430.PDF ] | |
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