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부품번호 | 78Q8430 기능 |
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기능 | 10/100 Ethernet MAC and PHY | ||
제조업체 | Teridian Semiconductor | ||
로고 | |||
전체 70 페이지수
www.DataSheet4U.com
78Q8430 10/100 Ethernet
MAC and PHY
Simplifying System Integration TM
DATA SHEET
DESCRIPTION
The Teridian 78Q8430 is a 10/100 Fast Ethernet
controller supporting multi-media offload. The
device is optimized for host processor offloading
and throughput enhancements for demanding
multi-media applications found in Set Top Box,
IP Video and Broadband Media Appliance
applications. The 78Q8430 seamlessly
interfaces to non-PCI processors through a
simplified pseudo SRAM-like Host Bus Interface
supporting 32/16/8 bit data bus widths.
Supported features include IEEE802.3x flow
control and full IEEE802.3 and 802.3u standards
compliance.
Supporting 10Base-T and 100Base-TX, the
transceiver provides Auto MDI-X cable
cross-over correction, AUTO Negotiation, Link
Configuration and full/half duplex support with
full duplex flow control. The line interface
requires only a dual 1:1 isolation transformer.
Numerous packet processing and IP address
resolution control functions are incorporated,
including an extensive set of Error Monitoring,
Reporting and Troubleshooting features. The
78Q8430 provides optimal 10/100 Ethernet
connectivity in demanding video streaming and
mixed-media applications.
BENEFITS
• Support for IEEE-802.3, IEEE-802.3u and
IEEE-802.3-2000 Annex 31.B
• Low host CPU utilization/overhead with
minimal software driver overhead and small
driver memory space requirements
• Improved packet processing, low latency and
low host CPU utilization
• Highest performance streaming Video over IP
• Optimized performance in mixed media
application such as video, data and voice
• Ease of use, faster development cycles, high
throughput
• Optimized power conservation with automatic
turn on when needed
• Reduced host CPU utilization and overhead
• Improved packet processing
• Optimized performance in mixed media
applications
March 2009
FEATURES
• Single chip 10Base-T/100Base-TX
IEEE-802.3 compliant MAC and PHY
Adaptive 32 kB SRAM FIFO memory
allocation between Tx and Rx paths
Queue independent user settable water
marks
Per queue status indication
• Address Resolution Controller (ARC)
Multiple perfect address filtering: 8 default
(max 12)
Wildcard address filtering, individual,
multicast and broadcast address
recognition and filtering
Positive/negative filtering and promiscuous
mode
• 64 kB JUMBO packet support
• QoS: 4 Transmit priority levels
• Non-PCI pseudo-SRAM Host Bus Interface
8-bit, 16-bit and 32-bit bus width
Big/little endian support for 16-bit/32-bit bus
widths
Asynchronous (100 MHz) and synchronous
(50 MHz) bus clock support
• Low power and flexible power supply
management
Power down/save
Wake on LAN (Magic Packet™, OnNow
packet)
Link status change
• Traffic Offload Engine Functionality
Transfer frame: APF & ICMP Echo
IP Firewall configuration: drop frames on
source IP address
IP Checksum
• Available in an industrial temperature range
(-40 °C to +85 °C)
• RoHS compliant (6/6) lead-free package
APPLICATIONS
• Satellite, cable and IPTV Set Top Boxes
• Multi Media Residential Gateways
• High Definition 1080p/1080i DTVs
• IP-PVR and video distribution systems
• Digital Video Recorders/Players
• Routers and IADs
• Video over IP system, IP-PBX
• IP Security Cameras / PVRs
• Low latency industrial automation
Rev. 1.2
© 2009 Teridian Semiconductor Corporation
1
78Q8430 Data Sheet
DwSw_w8.D4a3ta0S_he0e0t41U.com
7.6.3 Transmit Packet Status Register ................................................................................... 59
7.6.4 Transmit Producer Status .............................................................................................. 60
7.6.5 Receive Producer Status ............................................................................................... 60
7.6.6 Revision ID..................................................................................................................... 61
7.6.7 Configuration.................................................................................................................. 61
7.6.8 Receive to Transmit Transfer Register .......................................................................... 61
7.6.9 Frame Disposition Register ........................................................................................... 61
7.6.10 Receive FIRST BLOCK Status Register ....................................................................... 61
7.6.11 Receive Data Status Register........................................................................................ 62
7.6.12 BIST Control Register.................................................................................................... 62
7.6.13 BIST Bypass Mode Data Register ................................................................................. 63
7.6.14 Station Management Data Register .............................................................................. 63
7.6.15 Station Management Control and Address Register ..................................................... 63
7.6.16 PROM Data Register ..................................................................................................... 63
7.6.17 PROM Control Register ................................................................................................. 64
7.6.18 MAC Control Register.................................................................................................... 64
7.6.19 Count Data Register ...................................................................................................... 65
7.6.20 Counter Control Register ............................................................................................... 65
7.6.21 Counter Management Register...................................................................................... 66
7.6.22 Snoop Control Register ................................................................................................. 66
7.6.23 Interrupt Delay Count Register ...................................................................................... 66
7.6.24 Pause Delay Count Register ......................................................................................... 66
7.6.25 Host Not Responding Count Register ........................................................................... 67
7.6.26 Wake Up Status Register .............................................................................................. 67
7.6.27 Water Mark Values Register.......................................................................................... 67
7.6.28 Power Management Capabilities ................................................................................... 67
7.6.29 Power Management Control and Status Register ......................................................... 68
7.6.30 CAM Address Register .................................................................................................. 68
7.6.31 Rule Match Register ...................................................................................................... 69
7.6.32 Rule Control Register .................................................................................................... 69
7.6.33 Que Status Interrupt Register ........................................................................................ 70
7.6.34 Que Status Mask Register............................................................................................. 70
7.6.35 Overflow/Underrun Interrupt Register............................................................................ 71
7.6.36 Overflow/Underrun Mask Register................................................................................. 71
7.6.37 Transmit RMON Interrupt Register ................................................................................ 71
7.6.38 Transmit RMON Mask Register..................................................................................... 72
7.6.39 Receive RMON Interrupt Register ................................................................................. 72
7.6.40 Receive RMON Mask Register...................................................................................... 72
7.6.41 Host Interrupt Register................................................................................................... 72
7.6.42 Host Interrupt Mask Register ......................................................................................... 73
7.7 PHY Management Registers ..................................................................................................... 74
7.7.1 PHY Register Overview ................................................................................................. 74
7.7.2 PHY Control Register – MR0......................................................................................... 75
7.7.3 PHY Status Register – MR1 .......................................................................................... 76
7.7.4 PHY Identifier Registers – MR2, MR3 ........................................................................... 77
7.7.5 PHY Auto-Negotiation Advertisement Registers – MR4 ............................................... 77
7.7.6 PHY Auto-Negotiation Line Partner Ability Register – MR5 .......................................... 78
7.7.7 PHY Auto-Negotiation Expansion Register – MR6........................................................ 78
7.7.8 PHY Vendor Specific Register – MR16 ......................................................................... 79
7.7.9 PHY Interrupt Control / Status Register – MR17 ........................................................... 80
7.7.10 PHY Transceiver Control Register – MR19................................................................... 80
7.7.11 PHY Diagnostic Register – MR18.................................................................................. 81
7.7.12 PHY LED Configuration Register – MR23..................................................................... 81
7.7.13 PHY MDI / MDIX Control Register – MR24 ................................................................... 82
8 Isolation Transformers ..................................................................................................................... 83
9 Reference Crystal ............................................................................................................................. 83
10 System Bus Interface Schematic .................................................................................................... 84
11 Line Interface Schematic.................................................................................................................. 85
4 Rev. 1.2
4페이지 DS_8430_001
78Q843w0wDwa.DtaataSShheeete4Ut .com
1 Introduction
The Teridian 78Q8430 is a single chip 10Base-T/100Base-TX capable Fast Ethernet Media Access
Controller (MAC) and Physical Layer (PHY) transceiver. The device is optimized for video applications,
such as the Set Top Box (STB), and easily interfaces to available STB core processors, such as the
STi5100, STi5516, STi5514, ARM™ and Intel® based processors. The 78Q8430 is compliant with
applicable IEEE-802.3 standards. MAC and PHY configuration and status registers are provided as
specified by IEEE-802.3u.
The 78Q8430 operates over Category-5 Unshielded Twisted Pair (Cat-5 UTP) cabling in 100Base-TX
applications and over Cat-3 UTP in 10Base-T applications requiring only a dual 1:1 isolation transformer
interface to the copper media.
The Ethernet MAC section makes use of a 32 kB deep on-chip SRAM FIFO packet memory to adaptively buffer
transmit and receive data. SRAM memory can be dynamically allocated to either the transmit queues or the
receive queues as required to optimize throughput.
The host processor accesses the FIFO(s) using a simple asynchronous pseudo-SRAM like host bus interface.
A 32 bit wide bus is provided; the bus width can be pin-configured for 8-bit, 16-bit or 32-bit bus width at boot-up.
Big endian, little endian and mixed endian options are available in 32-bit operation; little endian is available for
16-bit operation. Different End-in variations are supported through internal circuitry with minimal user
intervention required.
The MAC interface logic may assert MEMWAIT during bus transactions, requesting wait states from the host
while critical internal data transfer completes. The MAC provides both half duplex and full duplex operation, as
well as support for full duplex flow control. Complete, portable device drivers for Linux®, OS20 and VxWorks®
are available.
The 78Q8430 operates from a single 3.3 V supply. Power down modes and power saving modes are
available. The 78Q8430 defaults to use an on-chip crystal oscillator. In this mode, a 25 MHz reference
crystal is connected between the XTLP and XTLN pins. Alternatively, an externally generated 25 MHz
clock can be connected to the XTLP pin. The chip will automatically configure itself to use the external
clock. In this mode of operation, a crystal is not required.
1.1 Systems Applications
Figure 1 presents an overview of the 78Q8430 in a block diagram.
8-bit/16-bit/32-bit
System Bus
Configuration
EEPROM Interface
(Optional)
JTAG Interface
TERIDIAN
78Q8430
Single Chip
10/100 Ethernet
Controller
LED
Link (Programmable)
LED
Activity (Programmable)
RJ45
1:1
Transformer
CAT 5
Cable
Figure 1: 78Q8430 Block Diagram
Rev. 1.2
7
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부품번호 | 상세설명 및 기능 | 제조사 |
78Q8430 | 10/100 Ethernet MAC and PHY | Teridian Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |