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MAX11210 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MAX11210
기능 Delta- Sigma ADCs
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MAX11210 데이터시트, 핀배열, 회로
19-5332; Rev 0; 6/10
www.DataSheet4U.com
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
General Description
The MAX11200/MAX11210 are ultra-low-power (< 300FA
active current), high-resolution, serial output ADCs.
These devices provide the highest resolution per unit
power in the industry, and are optimized for applications
that require very high dynamic range with low power,
such as sensors on a 4mA to 20mA industrial control
loop. Optional input buffers provide isolation of the sig-
nal inputs from the switched capacitor sampling network
allowing these converters to be used with high-imped-
ance sources without compromising available dynamic
range or linearity. The devices provide a high-accuracy
internal oscillator that requires no external components.
When used with the specified data rates, the internal
digital filter provides more than 100dB rejection of 50Hz
or 60Hz line noise. The devices are configurable using
the SPI™ interface and include four GPIOs that can be
used for external mux control. The MAX11210 includes
digital programmable gain of 1, 2, 4, 8, or 16.
The MAX11200/MAX11210 operate over the -40NC to
+85NC temperature range, and are available in a 16-pin
QSOP package.
Applications
Sensor Measurement (Temperature and
Pressure)
Portable Instrumentation
Battery Applications
Weigh Scales
Features
S 24.0-Bit ENOB at 5sps
20.9-Bit Noise-Free Resolution at 10sps
19-Bit Noise-Free Resolution at 120sps
S 570nVRMS Noise at 10sps, Q3.6VFS Input
S 1ppm INL (typ), 10ppm (max)
S No Missing Codes
S Ultra-Low Power Dissipation
Operating-Mode Current Drain < 300µA (max)
Sleep-Mode Current Drain < 0.4µA
S Programmable Gain (1, 2, 4, 8, or 16) (MAX11210)
S Four SPI-Controlled GPIOs for External Mux
Control
S 2.7V to 3.6V Analog Supply Voltage Range
S 1.7V to 3.6V Digital and I/O Supply Voltage Range
S Fully Differential Signal and Reference Inputs
S High-Impedance Inputs
Optional Input Buffers on Both Signal and
Reference Inputs
S Programmable Internal Clock or External Clock
Mode
S > 100dB (min) 50Hz/60Hz Rejection
S SPI, QSPI™, MICROWIRE™-Compatible Serial
Interface
S On-Demand Offset and Gain Self-Calibration and
System Calibration
S User-Programmable Offset and Gain Registers
S -40°C to +85°C Operating Temperature Range
S Q2kV ESD Protection
S Lead(Pb)-Free and RoHS-Compliant QSOP
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX11200EEE+
MAX11210EEE+
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
RESOLUTION
(BITS)
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
24 MAX11210
20 MAX11206
18 MAX11209
16 MAX11213
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
4-WIRE SPI,
16-PIN QSOP
MAX11200
MAX11207
MAX11211
MAX11203
2-WIRE SERIAL,
10-PIN μMAX
MAX11201 (with buffers)
MAX11202 (without buffers)
MAX11208
MAX11212
MAX11205
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.




MAX11210 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply
Digital Supply
Total Operating Current
VAVDD
VDVDD
AVDD + DVDD
Buffers disabled
Buffers enabled
2.7 3.6
1.7 3.6
235 300
255
V
V
FA
AVDD Sleep Current
AVDD Operating Current
Buffers disabled
Buffers enabled
0.15
185
205
2
235
FA
FA
DVDD Sleep Current
DVDD Operating Current
SPI TIMING CHARACTERISTICS
0.25
50
2
65
FA
FA
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to 1st SCLK Rise Setup
CS High to 17th SCLK Setup
fSCLK
tCP
tCH
tCL
tCSS0
tCSS1
60% duty cycle at 5MHz
5 MHz
200 ns
80 ns
80 ns
40 ns
40 ns
CS High After 16th SCLK Falling
Edge Hold
tCSH1
3 ns
CS Pulse-Width High
DIN to SCLK Setup
DIN Hold After SCLK
RDY/DOUT Transition Valid After
SCLK Fall
tCSW
tDS
tDH
tDOT
Output transition time, data changes on
falling edge of SCLK
40
40
0
ns
ns
ns
40 ns
RDY/DOUT Remains Valid After
SCLK Fall
tDOH
Output hold time allows for negative edge
data read
3
ns
RDY/DOUT Valid Before SCLK Rise
CS Rise to RDY/DOUT Disable
tDOL
tDOD
tDOL = tCL - tDOT
CLOAD = 20pF
40 ns
25 ns
CS Fall to RDY/DOUT Valid
tDOE
Default value of RDY is 1 for minimum
specification; maximum specification for
valid 0 on RDY/DOUT
0
40 ns
DATA Fetch
Maximum time after RDY asserts to read
tDF DATA register; tCNV is the time for one
conversion
0
tCNV -
60 x tCP
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
4   _______________________________________________________________________________________

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MAX11210 전자부품, 판매, 대치품
www.DataSheet4U.com
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
Functional Diagram
AVDD
DVDD
GND
AINP
AINN
REFP
REFN
TIMING
CLOCK GENERATOR
3RD-ORDER
DELTA-SIGMA
MODULATOR
DIGITAL FILTER
(SINC4)
PROGRAMMABLE
GAIN*
(1–16)
DIGITAL LOGIC
AND SERIAL-
INTERFACE
CONTROLLER
MAX11200
MAX11210
GPIO
*PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11210.
CLK
CS
SCLK
DIN
RDY/DOUT
GPIO1
GPIO2
GPIO3
GPIO4
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