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73S8014R 데이터시트 PDF




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부품번호 73S8014R 기능
기능 Smart Card Interface
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73S8014R 데이터시트, 핀배열, 회로
Simplifying System Integration™
www.DataSheet4U.com
73S8014R
Smart Card Interface
DATA SHEET
September 2008
DESCRIPTION
The Teridian 73S8014R is a single smart card (ICC) interface
circuit, firmware compatible with 8024-type devices for
configurations where only asynchronous cards must be
supported. It is derived from the 73S8024RN industry-
standard electrical interface. The 73S8014R has been
optimized to match most of the typical Set-Top-Box / A/V
Conditional Access applications. Optimization essentially
involved a smaller pin-count, support for single I/O, and
maximum card current of 65mA (ISO-7816 / EMV
compliance).
The 73S8014R interfaces with the host processor through the
same bus (digital I/Os) as the 73S8024RN, which is
compatible with any other 8024-type IC. As a result, the
73S8014R is a very attractive cost-reduction path from
traditional 8024 ICs. The 73S8014R has been designed to
provide full electrical compliance with ISO 7816-3 and EMV
4.0 specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to an externally
supplied clock signal.
The 73S8014R incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO regulator is
powered by a dedicated power supply input VPC. Digital
circuitry is powered separately by a digital power supply VDD.
With its embedded LDO regulator, the 73S8024RN is a
cost-effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Emergency card deactivation is initiated upon card extraction
or upon any fault detected by the protection circuitry. The
fault can be a card over-current, VCC undervoltage or power
supply fault (VDD). The card over-current circuitry is a true
current detection function, as opposed to VCC voltage drop
detection, as usually implemented in non-Teridian 8024
interface ICs.
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor network. It allows
automated card deactivation at a customized VDD voltage
threshold value. It can be used, for instance, to match the
system controller operating voltage range.
APPLICATIONS
Set-Top-Box Conditional Access and Pay-per-View
General purpose smart card readers
ADVANTAGES
Same advantages as the Teridian 73S80xxR family:
ƒ VCC card generated by an LDO regulator
ƒ Very low power dissipation (saves up to 1/2W)
ƒ Fewer external components are required
ƒ Better noise performance
True card over-current detection
Firmware compatibility with all 8024 ICs
Small format 20SO package
FEATURES
Card Interface:
ƒ Complies with ISO 7816-3 and EMV 4.0
ƒ Supports 3V / 5V cards
ƒ ISO 7816-3 Activation / Deactivation sequencer
ƒ Automated deactivation upon hardware fault (i.e. upon
drop on VDD power supply or card overcurrent)
ƒ The VDD voltage supervisor threshold value (fault) can
be externally adjusted
ƒ Over-current detection 130mA max
ƒ Card CLK clock frequency up to 20MHz
System Controller Interface:
ƒ 3 Digital inputs control the card activation /
deactivation, card reset and card voltage
ƒ 2 Digital inputs control the card clock frequency
ƒ 1 Digital output, interrupt to the system controller,
reports to the host the card presence and faults
ƒ Crystal oscillator or host clock, up to 27MHz
Regulator Power Supply:
ƒ 4.75V to 5.5V
Digital Interfacing: 2.7V to 5.5V
6kV ESD protection on the card interface
Package: SO 20-pin
RoHS compliant (6/6) lead-free package
Rev. 1.0
© 2008 Teridian Semiconductor Corporation
1




73S8014R pdf, 반도체, 판매, 대치품
73S8014R Data Sheet
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Figures
Figure 1: 73S8014R Block Diagram .......................................................................................................................... 2 
Figure 2: 73S8014R 20-SOP Pin Out........................................................................................................................ 5 
Figure 3: 73S8014R – Typical Application Schematic ............................................................................................ 15 
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low ............................................................. 18 
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low............................................................. 19 
Figure 6: Deactivation Sequence ............................................................................................................................ 19 
Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20 
Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21 
Figure 9: I/O – I/OUC Delays – Timing Diagram ..................................................................................................... 21 
Figure 10: Open Drain type – OFF .......................................................................................................................... 22 
Figure 11: Power Input/Output Circuit, VDD, VPC, VCC ........................................................................................ 22 
Figure 12: Smart Card CLK Driver Circuit ............................................................................................................... 23 
Figure 13: Smart Card RST Driver Circuit ............................................................................................................... 23 
Figure 14: Smart Card IO Interface Circuit .............................................................................................................. 24 
Figure 15: Smart Card IOUC Interface Circuit......................................................................................................... 24 
Figure 16: General Input Circuit .............................................................................................................................. 25 
Figure 17: Oscillator Circuit ..................................................................................................................................... 25 
Figure 18: VDDF_ADJ ............................................................................................................................................. 26 
Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27 
Tables
Table 1: 73S8014R 20-Pin SOP Pin Definitions ....................................................................................................... 6 
Table 2: Absolute Maximum Device Ratings............................................................................................................. 8 
Table 3: Recommended Operating Conditions ......................................................................................................... 8 
Table 4: Package Thermal Parameters..................................................................................................................... 9 
Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9 
Table 6: Digital Signals Characteristics ................................................................................................................... 11 
Table 7: DC Characteristics..................................................................................................................................... 12 
Table 8: Voltage Fault Detection Circuits ................................................................................................................ 13 
Table 9: Order Numbers and Packaging Marks ...................................................................................................... 28 
4 Rev. 1.0

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73S8014R 전자부품, 판매, 대치품
DS_8014R_012
www.DataSheet4U.com
73S8014R Data Sheet
Miscellaneous Inputs and Outputs
XTALIN
9
Figure 17
XTALOUT
10
Figure 17
VDDF_ADJ 12
Figure 18
Power Supply and Ground
VDD
13 PSO
VPC
GND
4
8, 11
PSO
GND
Figure 11
Figure 11
Crystal oscillator input: can either be connected to crystal or
driven as a source for the card clock. Note: When not using the
crystal, the capacitors must be removed.
Crystal oscillator output: connected to crystal. Left open if
XTALIN is being used as external clock input. Note: When not
using the crystal, the capacitors must be removed.
VDD fault threshold adjustment input: this pin can be used to adjust
the VDDF value (that controls deactivation of the card). Must be
left open if unused.
System interface supply voltage and supply voltage for internal
circuitry.
LDO regulator power supply source.
Digital ground.
Rev. 1.0
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
73S8014R

Smart Card Interface

Teridian Semiconductor
Teridian Semiconductor
73S8014RN

Smart Card Interface

Teridian Semiconductor
Teridian Semiconductor

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