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부품번호 | 73S8010R 기능 |
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기능 | Low Cost Smart Card Interface | ||
제조업체 | Teridian Semiconductor | ||
로고 | |||
전체 25 페이지수
Simplifying System Integration™
DS_8010R_022
www.DataSheet4U.com
73S8010R
Low Cost Smart Card Interface
DATA SHEET
August 2009
DESCRIPTION
The Teridian 73S8010R is a single smart card
interface IC that provides full electrical compliance
with ISO-7816-3 and EMV 4.0 (EMV2000)
specifications.
Interfacing with the host is done through the two-wire
I2C bus and one interrupt output to inform the
system controller of the card presence and faults.
The card clock signal can be generated by an
on-chip oscillator using an external crystal, or by
connection to a clock signal.
The Teridian 73S8010R incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level-shifters drive the card signals with
the selected card voltage (3 V or 5 V), coming from an
internal Low Drop-Out (LDO) voltage regulator. This
LDO regulator is powered by a dedicated power
supply input, VPC. Digital circuitry is separately
powered by a digital power supply, VDD.
With its embedded LDO regulator, the Teridian
73S8010R is a cost-effective solution for any
application where a 5 V (typically -5% +10%) power
supply is available. Hardware support for auxiliary
I/O lines, C4 / C8 contacts is provided.
Emergency card deactivation is initiated upon
card extraction or upon any fault generated by
the protection circuitry. The fault can be a card
over-current, a VDD (digital power supply), a VPC
(regulator power supply), a VCC (card power supply)
or an over-heating fault.
The card over-current circuitry is a true current detect
function, as opposed to VCC voltage drop detection, as
usually implemented in ICC interface ICs.
The VDD voltage fault has a threshold voltage that
can be adjusted with an external resistor or resistor
network. It allows automated card deactivation at a
customized VDD voltage threshold value. It can be
used, for instance, to match the system controller
operating voltage range.
APPLICATIONS
• Set-Top-Box Conditional Access and
Pay-per-View
• Point of Sales & Transaction Terminals
• Control Access & Identification
• Multiple card and SAM reader configurations
ADVANTAGES
• Single smart card interface
• IC firmware compatible with TDA8020
• Traditional step-up converter is replaced by
an LDO regulator
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90 mA supplied to
the card)
• Small format (5x5x0.8 mm) QFN32 package option
• True card over-current detection
FEATURES
• Card Interface
• Complies with ISO-7816-3 and EMV 4.0
• An LDO voltage regulator provides 3 V / 5 V to
the card from an external power supply input
• ISO-7816-3 Activation / Deactivation
sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry
• Protection includes 3 voltage supervisors
that detect voltage drops on VCC card and
on power supplies VDD and VPC
• Over-current detection 150 mA max
• 1 card detection input
• Auxiliary I/O lines, for C4 / C8 contact
signals
• Host Interface
• Fast mode, 400 kbps I2C slave bus
• 8 possible devices in parallel
• One control register and one status
register
• Interrupt output to the host for fault
detection
• Crystal oscillator or host clock, up to 27 MHz
• 6 kV ESD protection on the card interface
• SO28 or QFN32 package
Rev. 1.6
© 2009 Teridian Semiconductor Corporation
1
73S8010R Data Sheet
DSw_w8w0.1D0atRaS_he0e2t42U.com
Figures
Figure 1: 73S8010R Block Diagram......................................................................................................... 2
Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5
Figure 3: 73S8010R 28-Pin SO Pinout..................................................................................................... 5
Figure 4: Typical 73S8010R Application Schematic ............................................................................... 13
Figure 5: I2C Bus Write Protocol ............................................................................................................ 15
Figure 6: I2C Bus Read Protocol ............................................................................................................ 16
Figure 7: I2C Bus Timing Diagram.......................................................................................................... 16
Figure 8: Activation Sequence ............................................................................................................... 19
Figure 9: Deactivation Sequence ........................................................................................................... 20
Figure 10: Interrupt operation due to Fault and Status Conditions .......................................................... 20
Figure 11: Warm Reset Operation ......................................................................................................... 21
Figure 12: I/O Timing Diagram............................................................................................................... 21
Figure 13: 32-pin QFN Package Dimensions ......................................................................................... 22
Figure 14: 28-Pin SO Package Dimensions ........................................................................................... 23
Tables
Table 1: 73S8010R Pin Definitions .......................................................................................................... 6
Table 2: Absolute Maximum Device Ratings ............................................................................................ 8
Table 3: Recommended Operating Conditions......................................................................................... 8
Table 4: DC Smart Card Interface Requirements ..................................................................................... 9
Table 5: Digital Signals Characteristics .................................................................................................. 11
Table 6: DC Characteristics ................................................................................................................... 11
Table 7: I2C Characteristics ................................................................................................................... 12
Table 8: Voltage / Temperature Fault Detection Circuits......................................................................... 12
Table 9: Device Address Selection ........................................................................................................ 14
Table 10: Control Register Description................................................................................................... 14
Table 11: Card Clock Rate Selection ..................................................................................................... 14
Table 12: Status Register Description .................................................................................................... 15
Table 13: I2C Bus Timing Parameters ................................................................................................... 16
Table 14: Choice of VCC Pin Capacitor ................................................................................................. 18
Table 15: Card Clock Divisor Options .................................................................................................... 18
Table 16: Order Numbers and Packaging Marks.................................................................................... 24
4 Rev. 1.6
4페이지 DS_8010R_022
73S8010RwwDwa.DtaataSShheeete4Ut .com
Pin
Name
Pin
(SO28)
Microcontroller Interface
INT 23
SAD0
SAD1
SAD2
1
2
3
Pin
(QFN32)
22
29
30
31
Type
Description
O Interrupt output signal (negative assertion) to the
processor. A 20 kΩ pull up to VDD is provided
internally.
I Serial device address bits. Digital inputs for address
I selection that allows for the connection of up to 8
I devices in parallel. Address selections is as follows:
SAD2 SAD1 SAD0
000
001
010
011
100
101
110
111
(7 bit) I2C
Address
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
SCL
SDA
I/OUC
AUX1UC
AUX2UC
Pins SAD0 and SAD1 are internally pulled down and
SAD2 is internally pulled up. The default address
when unconnected is 0x48.
19 18 I I2C clock signal input.
20 19 I/O I2C bi-directional serial data signal.
26 26 IO System controller data I/O to/from the card. Includes
an internal pull-up resistor to VDD.
27 27 IO System controller auxiliary data I/O to/from the card.
Includes an internal pull-up resistor to VDD.
28 28 IO System controller auxiliary data I/O to/from the card.
Includes an internal pull-up resistor to VDD.
Rev. 1.6
7
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부품번호 | 상세설명 및 기능 | 제조사 |
73S8010C | Smart Card Interface | Teridian Semiconductor |
73S8010R | Low Cost Smart Card Interface | Teridian Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |