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PDF 71M6511H Data sheet ( Hoja de datos )
| Número de pieza | 71M6511H | |
| Descripción | Single-Phase Energy Meter IC | |
| Fabricantes | TERIDIAN Semiconductor | |
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71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
GENERAL DESCRIPTION
The TERIDIAN 71M6511 is a highly integrated SOC with an MPU core,
RTC, FLASH and LCD driver. TERIDIAN’s patented Single Converter
Technology with a 22-bit delta-sigma ADC, 3 analog inputs, digital
temperature compensation, precision voltage reference and 32-bit
computation engine (CE) supports a wide range of single-phase metering
applications with very few low cost external components. A 32kHz crystal
time base for the entire system and internal battery backup support for RAM
and RTC further reduce system cost.
Maximum design flexibility is supported with multiple UARTs, I2C, a power
fail comparator, a 5V LCD charge pump, up to 12 DIO pins and an in-
system programmable FLASH. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction residential/commercial
meter applications requiring multiple voltage/current inputs and complex
LCD or DIO configurations.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards.
LIVE CT/SHUNT
NEUT
LOAD
POWER SUPPLY
V or I
AMR
IR
POWER
FAULT
32 kHz
CONVERTER
IA
VA
IB
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
RX
SENSE RX
DRIVE TX
COMPARATOR
V1
OSC/PLL
XIN
XOUT
V3.3A V3.3D GNDA GNDD
5V BOOST
TERIDIAN
VDRV
71M6511 REGULATOR
TEMP
SENSOR
RAM
FLASH
VBAT
V2.5
LCD DRIVER
DIO, PULSE
VLCD
COM0..3
SEG0..19
SEG 24..32
DIO 0..11
COMPUTE
ENGINE
SEG 32..41
DIO 12..21
MPU
RTC
TIMERS
ICE
BATTERY
3V/5V LCD
88.88.8888
EEPROM
TEST PULSES
7/20/2007
FEATURES
Wh accuracy over temperature and
2000:1 range
< 0.1% -- 71M6511H,
<0.5% -- 71M6511
Exceeds IEC62053 / ANSIC12.20.
Voltage reference
< 10ppm/°C -- 71M6511H,
< 50ppm/°C -- 71M6511
Three sensor inputs - VDD
referenced
Low jitter Wh/VARh pulse outputs
Pulse count for pulse outputs
Four-quadrant metering
Voltage/current angle
Line frequency count for RTC
Digital temperature compensation
Sag detection
Independent 32-bit compute engine
40-70Hz line frequency range with
same calibration
Phase compensation (±7°)
Battery Backup for RAM and RTC
22mW @3.3V, 7.2µW back up
Flash memory option with security
22-bit delta-sigma ADC
8-bit MPU (80515) - 1 clock cycle per
instruction
LCD driver (≤128 pixels)
High speed SSI serial output
RTC for time-of-use functions
Hardware watchdog timer
Up to 12 general purpose I/O pins
64KB Flash, 7KB RAM
Two UARTs for IR and AMR
64-lead LQFP package
Page: 1 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
V2.6
1 page  
www.DataSheet4U.com
71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Figure 27: Meter Accuracy over Harmonics at 240V, 30A .............................................................................75
Figure 28: Typical Meter Accuracy over Temperature Relative to 25°C (w/ Temperature
Compensation) .....................................................................................................................75
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) .........................................................76
Figure 30: Resistive Shunt (left), Rogowski Coil (right) ..................................................................................76
Figure 31: Crystal Frequency over Temperature ...........................................................................................77
Figure 32: Crystal Compensation...................................................................................................................78
Figure 33: Connecting LCDs..........................................................................................................................79
Figure 34: LCD Boost Circuit .........................................................................................................................79
Figure 35: EEPROM Connection ...................................................................................................................80
Figure 36: Interfacing RX to a 0-5V Signal.....................................................................................................80
Figure 37: Connection for Optical Components .............................................................................................81
Figure 38: Voltage Divider for V1 ...................................................................................................................81
Figure 39: External Components for RESETZ ...............................................................................................82
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles .............................................................8
Table 2: Channel control based on MUX_DIV and FIR_LEN...........................................................................9
Table 3: CE DRAM Locations for ADC Results .............................................................................................12
Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) ...............12
Table 5: Stretch Memory Cycle Width............................................................................................................16
Table 6: Internal Data Memory Map...............................................................................................................17
Table 7: Special Function Registers Locations ..............................................................................................17
Table 8: Special Function Registers Reset Values ........................................................................................18
Table 9: PSW Register Flags.........................................................................................................................19
Table 10: PSW bit functions...........................................................................................................................19
Table 11: Port Registers ................................................................................................................................20
Table 12: Special Function Registers ............................................................................................................21
Table 13: Baud Rate Generation ...................................................................................................................22
Table 14: UART Modes .................................................................................................................................22
Table 15: The S0CON Register .....................................................................................................................22
Table 16: The S1CON register ......................................................................................................................23
Table 17: The S0CON Bit Functions..............................................................................................................23
Table 18: The S1CON Bit Functions..............................................................................................................24
Table 19: The TMOD Register.......................................................................................................................24
Table 20: TMOD Register Bit Description ......................................................................................................25
Table 21: Timers/Counters Mode Description................................................................................................25
Table 22: The TCON Register .......................................................................................................................25
Table 23: The TCON Register Bit Functions..................................................................................................26
Table 24: Timer Modes ..................................................................................................................................26
Table 25: The PCON Register .......................................................................................................................26
Table 26: The IEN0 Register (see also Table 34) ..........................................................................................27
Table 27: The IEN0 Bit Functions (see also Table 34)...................................................................................27
Table 28: The IEN1 Register (see also Tables 35/36) ...................................................................................27
Table 29: The IEN1 Bit Functions (see also Tables 35/36)............................................................................27
Table 30: The IP0 Register (see also Table 46) ............................................................................................28
Table 31: The IP0 bit Functions (see also Table 46)......................................................................................28
Table 32: The WDTREL Register ..................................................................................................................28
Page: 5 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
V2.6
5 Page 
www.DataSheet4U.com
71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
VREF VBIAS
IA
VA
IB
MUX
VBIAS
TEMP
MUX
MUX
CTRL
EQU
MUX_ALT
MUX_DIV
VREF
CHOP_EN
VREF_DIS
CK32
∆Σ ADC
CONVERTER
V3P3A
-
+
VREF
Figure 3: AFE Block Diagram
FIR
FILTER
FIR_LEN
Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
• Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
• Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
• 90° phase shifter (for VAR calculations).
• Pulse generation.
• Monitoring of the input signal frequency (for frequency and phase information).
• Monitoring of the input signal amplitude (for sag detection).
• Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code
pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the
multiplexer cycle ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding re-
gisters are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed,
depending on the frequency of CKMPU.
Table 3 shows the CE DRAM addresses allocated to analog inputs from the AFE.
Page: 11 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
V2.6
11 Page | ||
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