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PDF NB4L7210 Data sheet ( Hoja de datos )

Número de pieza NB4L7210
Descripción 2.5V/3.3V Differential 2x10 Crosspoint Clock Driver
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NB4L7210
2.5V/3.3V Differential 2x10
Crosspoint Clock Driver
with SDI Programmable
Output Selects
The NB4L7210 is a Clock input crosspoint fanout distribution
device selecting between one of two input clocks on each of the 10
differential output pairs. A 10 Bit Serial Data Interface programs each
output MUX to asynchronously select either Input clock.
CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or
LVDS signal levels and incorporate an internal 50 ohms on die
termination resistors. SCLK, SDATA, and SLOAD input can accept
single ended LVPECL, CML, LVCMOS, LVTTL signals levels.
SCLK and SDATA inputs operate up to 20 MHz. SLOAD input
loads and latches the output select data. The SDATAOUT pin permits
cascading multiple devices. Outputs are optimized for minimal
output−to−output skew and low jitter.
Features
Typical Input Clock Frequency > 2 GHz
200 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Output to Output Skew 150 ps
Additive RMS Phase Jitter of 0.2 ps
Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
Differential LVPECL Output Level (Typ 700 mV Peak−to−Peak)
Low Profile 8x8 mm, 52 QFN Package
10GE WAN: 155.52 MHz / 622.08 MHz
10GE LAN: 161.1328 MHz
These are Pb−Free Devices*
www.onsemi.com
1 52
QFN52
MN SUFFIX
CASE 485M
MARKING
DIAGRAM*
52
1
NB4L
7210
AWLYYWWG
NB4L7210
A
WL
YY
WW
G
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK0
CLK0
CLK0b
VTCLK0b
Q0
Q0b
Q1
Q1b
VTCLK1
CLK1
CLK1b
VTCLK1b
VCC
VEE
SCLK
SDATA
SLOAD
Q8
Q8b
Q9
Q9b
SDATAOUT
Figure 1. Functional Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1
Publication Order Number:
NB4L7210/D

1 page




NB4L7210 pdf
NB4L7210
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 6))
Symbol
Characteristic
Min Typ
Max Unit
VOUTPP
tPLH,
tPHL
Output Voltage Amplitude @ VINPPmin (See Figure 9)
fin = 100 MHz
fin = 1 GHz
Propagation Delay to (See Figure 9)
CLK/CLK to Qx/Qx (Note 7)
SCLK to SDATAOUT Measured at 1.5 V
650 800 875 mV
530 790 960
610 725 875 ps
6.5 20 30.8 ns
tSKEW
Duty Cycle Skew (Note 8)
Within −Device Skew
Device to Device Skew (Note 8)
−5 2 10 ps
0 5 35
0 20 200
ts Setup Time
SDATA to SCLK Measured at 1.5 V
SCLK to SLOAD+ Measured at 1.5 V
−150
1000
−115
ps
Th Hold Time
SDATA to SCLK 325 345 365 ps
PWmin Minimum Pulse Width
SLOAD
2.0
ns
tJIT(Ø)
RMS Phase Jitter, Integration Range 12 KHz to 20 MHz
@155.52 MHz
@ 622.08 MHz
See Fig 10
See Fig 11
fs
tJITTER
TIE Rj (10,000 Cycles)
@155.52 MHz
@ 622.08 MHz
Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)
1.7 ps
0.63
3.9
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration, measured Single−ended on each input)
150
750
1200
mV
tr , tf Output Risetime and Falltime
Qx/Qx (20% to 80%) 120 185 260 ps
SDATAOUT (0.8 V − 2.0 V) 0.88 10
15 ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Measured by forcing VINPP (Typ 750 mVPP) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50 W to VCC − 2.0 V (See Figure 16).
SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND.
7. Measured from the input pair crosspoint to each single output pair crosspoint.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
9. 155.52 MHz @ 750 mVPP input on measured output, 161.13 MHz @ 850 mVPP input on all other others.
www.onsemi.com
5

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NB4L7210 arduino
NB4L7210
PACKAGE DIMENSIONS
D
ÉÉÉÉPIN ONE
ÉÉÉÉÉÉÉÉÉÉÉÉREFERENCE
QFN52 8x8, 0.5P
CASE 485M
ISSUE C
A
B
E
2X
0.15 C
2X
0.15 C
0.10 C
0.08 C
SEATING PLANE
A1
52 X L
14
13
A2
A3 REF
D2
26
27
A
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A2 0.60 0.80
A3 0.20 REF
b 0.18 0.30
D 8.00 BSC
D2 6.50 6.80
E 8.00 BSC
E2 6.50 6.80
e 0.50 BSC
K 0.20 ---
L 0.30 0.50
RECOMMENDED
SOLDERING FOOTPRINT
8.30
6.75
52X
0.62
52 X K
1
52
e
E2
39
40
52 X b NOTE 3
0.10 C A B
0.05 C
PKG
OUTLINE
0.50
PITCH
6.75 8.30
52X
0.30
DIMENSIONS: MILLIMETERS
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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11
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