PDF NB4N111K Data sheet ( Hoja de datos )

Número de pieza	NB4N111K
Descripción	3.3V Differential In 1:10 Differential Fanout Clock Driver
Fabricantes	ON Semiconductor
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No Preview Available ! NB4N111K www.DataSheet4U.com 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output Description The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single−ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Outputs can interface with LVDS with proper termination (See Figure 15). The NB4N111K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N111K’s performance to distribute low skew clocks across the backplane or the motherboard. Features • Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and 400 MHz • 340 ps Typical Rise and Fall Times • 800 ps Typical Propagation Delay • Dtpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair • <1 ps RMS Additive Clock jitter • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V • Differential HCSL Output Level or LVDS with Proper Termination • These are Pb−Free Devices http://onsemi.com 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM* 32 1 NB4N 111K AWLYYWWG A = Assembly Site WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. VTCLK CLK CLK VTCLK VCC GND Q0 Q0 Q1 Q1 RREF Q8 Q8 Q9 IREF Q9 Figure 1. Pin Configuration (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 4 1 Publication Order Number: NB4N111K/D 1 page NB4N111K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +70°C (Note 7) Symbol Characteristic VOUTPP tPLH, tPHL DtPLH, DtPHL tSKEW Output Voltage Amplitude (@ VINPPmin) Propagation Delay to (See Figure 3) fin = 400 MHz CLK/CLK to Qx/Qx Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) Duty Cycle Skew (Note 9) Within−Device Skew Device−to−Device Skew (Note 10) tJITTER Vcross DVcross tr, tf RMS Random Clock Jitter (Note 11) Absolute Crossing Magnitude Voltage Variation in Magnitude of Vcross Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) fin = 400 MHz Qx, Qx Min 550 250 175 www.DataSheet4U.com Typ Max Unit 725 1000 mV 800 1100 ps 100 ps 20 ps 100 ps 150 ps 1 ps 550 mV 150 mV 340 700 ps Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single−Ended) (See Figure 4) Qx, Qx 125 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with all outputs loaded 50 W to GND, see Figure 9. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+. 10. Skew is measured between outputs under identical transition @ 400 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK CLK Q tPLH VINPP = VIH(CLK) − VIL(CLK) = VIH(CLK) − VIL(CLK) tPHL VOUTPP = VOH(Q) − VOL(Q) = VOH(Q) − VOL(Q) Q DtPLH DtPHL Figure 3. AC Reference Measurement http://onsemi.com 5 5 Page

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