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73201-364LF 데이터시트 PDF




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기능 SKY73201-364LF
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73201-364LF 데이터시트, 핀배열, 회로
www.DataSheet4U.com
preliminary data sheet
SKY73201-364LF, SKY73202-364LF: Programmable
1–28 MHz 6th Order Low Pass Filters
Applications
l H igh-performance direct conversion receivers
• Software-defined radio basebands
• High-definition television tuners
• Medical imaging
• Flexible anti-aliasing and reconstruction filters
Features
• 6th order Butterworth low pass filter
• Exceptionally high dynamic range
• Auto-calibrated with clock reference, 20 MHz or 40 MHz nominal
• Programmable in steps from 1–28 MHz
• Nominal low pass filter step size of 1 MHz
• Single or dual channel configuration
• Serial bus control
• 5 x 5 mm QFN package
l L ead (Pb)-free, RoHS-compliant, and Green™,
MSL-3 @ 260 °C per JEDEC J-STD-020
NEW Skyworks Green™ products are RoHS (Restriction
of Hazardous Substances)-compliant, conform to
the EIA/EICTA/JEITA Joint Industry Guide (JIG)
Level A guidelines, are halogen free according to
IEC-61249-2-21, and contain <1,000 ppm antimony
trioxide in polymeric materials.
Description
The SKY73201-364LF & SKY73202-364LF are high-performance,
programmable, monolithic, clock-referenced low-pass filters.
They are configured as a 6th order Butterworth to provide
extremely high stop-band isolation while maximizing pass-band
flatness and minimizing group delay distortion. The corner
frequency is programmable, via the 3-wire Serial Peripheral
Interface (SPI), in steps, from 1–28 MHz, when a 20 MHz or
40 MHz reference is used. Nearly ideal Butterworth performance
is maintained over temperature and process via a proprietary
internal calibration circuit which derives its timing accuracy from
the reference clock. Nominal reference clock frequencies of
20 MHz or 40 MHz are recommended to meet the specifications
outlined in this data sheet but other reference clock frequencies
can be accommodated with appropriate changes to the
control register settings. The corner frequency range can be
extended beyond 28 MHz by the use of alternate reference clock
frequencies and modified control register settings. Please contact
Skyworks Solutions applications engineering for assistance with
your requirements.
Additionally, the SKY73201-364LF & SKY73202-364LF offer excel-
lent linearity and input noise level (83 dB SNR at 1 MHz corner
setting), making them suitable for extremely high dynamic range
applications such as adjacent channel rejection filters in direct con-
version receivers. The I/O interface is fully differential, but may also
be used single-ended, and on-chip input/output drivers allow easy
integration between modern system components such as mixers,
data converters, and variable gain amplifiers.
The dual configuration of SKY73202 offers the convenience of having
two channels (such as the I and Q in vector demodulation) with
closely matched characteristics that track each other. Both filters
are programmed to the same settings by the common SPI interface.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200755 Rev. C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • October 1, 2008
1




73201-364LF pdf, 반도체, 판매, 대치품
preliminary Data Sheet • Sky73201-364LF, SKY73202-364LF
Typical Performance Data
VDD = 3.3 V, T = 25 °C, unless otherwise noted
1 MHz
6 MHz
11 MHz
16 MHz
21 MHz
26 MHz
20
2 MHz
7 MHz
12 MHz
17 MHz
22 MHz
27 MHz
3 MHz
8 MHz
13 MHz
18 MHz
23 MHz
28 MHz
4 MHz
9 MHz
14 MHz
19 MHz
24 MHz
5 MHz
10 MHz
15 MHz
20 MHz
25 MHz
www.DataSheet4U.com
0
-20
-40
-60
-80
-100
0
20 40 60 80 100 120
Frequency (MHz)
programmable Filter amplitude response
140
Group Delay (ns)
Magnitude (dB)
0
-10
-20
-30
-40
160
140
120
100
80
-50 60
-60 40
-70
0
20
5 10 15 20 25 30 35
Frequency (MHz)
Filter response with 3 dB Cutoff tuned to 8 mhz
Group Delay (ns)
Magnitude (dB)
0
120
-5 100
-10
-15 80
-20 60
-25
-30 40
-35
-40
-45
0
20
0
5 10 15 20 25 30 35
Frequency (MHz)
Filter response with 3 dB Cutoff tuned to 14 mhz
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
4 October 1, 2008 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • 200755 Rev. C

4페이지










73201-364LF 전자부품, 판매, 대치품
preliminary Data Sheet • Sky73201-364LF, SKY73202-364LF
www.DataSheet4U.com
Serial I/O Interface Information
The primary control interface is a three-wire bidirectional serial
interface. The interface operates as slowly as DC, and as fast as
100 Mbps. The three interface signals are SPI_CLK, SPI_DATA
and SPI_LE. The serial data bits are latched into the serial inter-
face on each rising edge of SPI_CLK. Data is latched into the
target register by the rising edge of SPI_LE. There are 3 func-
tional data registers, each containing 8 data bits. Each register
is independent and can be read or written in any order.
Each serial interface transaction, read/write, consists of 16 bits:
1 start bit, 2 reserved bits (0s), 1 read/write bit, 4 address bits
followed by 8 data bits. See Figure 1.
ADDRESS Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Start bit Reserved Reserved Read/
= 1 = 0 = 0 write
A3
A2
A1
A0
DATA Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 1. SPI Transaction Bit Definitions
T1 T2 T3
T4
SPI_CLK
SPI_LE
SPI_DATA
start Reserved R/W A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CAL_EN
Register read back is optional and is not required for normal function.
*R/W Bit Sets Direction of Data Line for Serial Read-back; Read = 0, Write = 1.
** Cal_EN Line is toggled AFTER ALL registers are written.
T5
Figure 2. SPI Register Configuration Timing Diagram
SPI Interface Timing Requirements
Parameter
Description Min
T1
Setup time LE to DATA
5
T2
Hold time CLK to DATA
5
T3
Setup time DATA to CLK
5
T4
LE Width
10
T5
LE to CalEn
10
Unit
ns
ns
ns
ns
ns
The setup and hold timing requirements are shown in Figure 2
and the SPI Interface Timing Requirements table. The SPI_LE line
must have a setup time of (T1) before the first clock edge. All
data bits must be held for a minimum of (T2) after the rising clock
edge. The minimum setup time for any bit edge is (T3) before
the rising edge of SPI_CLK. The SPI_LE signal must be held for
a minimum time (T4) between transactions and held high when
other SPI devices on the bus are active. The CalEn signal must
be toggled after all the register configuration is complete in order
to initiate the auto calibration feature. The configuration of all the
registers will require approximately 50 SPI_CLK cycles and the
auto calibration will require approximately 50 Ref_Clk cycles. The
TUNED pin will go high at the successful completion of auto cali-
bration and may be used to disable the reference clock source.
On power up, all registers will be cleared to 0 and the filter’s
inputs and outputs will be in an isolated state. All registers retain
their data when ENABLE is held to the standby state, ground. In
this condition the filter inputs and outputs will be in an isolated
state. When ENABLE is taken to VDD, inputs and outputs will be
in an isolated state until CalEn is toggled and auto calibration has
completed.
SPI Register Map Detail
SKY73201 & SKY73202 Configuration Register Map
Address
0
1
2
Bit Field
[2:0]
[7:3]
[4:0]
[6:5]
[7]
[4:0]
[7:5]
Register Name
ResSkewCtr
ResDacCtr
ResCtr
BandSel
Reserved
GainCtr
Reserved
Usage
Corner frequency fine tune
Calibration constant
Calibration constant
Sets filter corner frequency
Write to zero
Sets filter gain
Write to zero
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200755 Rev. C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • October 1, 2008
7

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73201-364LF

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