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PDF UM10114 Data sheet ( Hoja de datos )
| Número de pieza | UM10114 | |
| Descripción | LPC21xx and LPC22xx User manual | |
| Fabricantes | NXP Semiconductors | |
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UM10114
LPC21xx and LPC22xx User manual
Rev. 03 — 2 April 2008
www.DataSheet4U.com
User manual
Document information
Info Content
Keywords
LPC2109/00, LPC2109/01, LPC2119, LPC2119/01, LPC2129,
LPC2129/01, LPC2114, LPC2114/01, LPC2124, LPC2124/01, LPC2194,
LPC2194/01, LPC2210, LPC2220, LPC2210/01, LPC2212, LPC2212/01,
LPC2214, LPC2214/01, LPC2290, LPC2290/01, LPC2292, LPC2292/01,
LPC2294, LPC2294/01, ARM, ARM7, 32-bit, Microcontroller
Abstract
User manual for LPC2109/19/29/14/24/94 and
LPC2210/20/12/14/90/92/94 including /01 parts
1 page  
NXP Semiconductors
UM10114www.DataSheet4U.com
Chapter 1: Introductory information
• Up to 12 edge or level sensitive external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL with a
possible input frequency of 10 MHz to 25 MHz and a settling time of 100 ms.
• For flashless LPC2210/20/90 only: 60 MHz (LPC2210/90), 72 MHz (LPC2290/01), or
75 MHz (LPC2210/01 and LPC2220) maximum CPU clock available from
programmable on-chip Phase-Locked Loop (PLL) with settling time of 100 μs.
• On-chip integrated oscillator operates with an external crystal in the range from
1 MHz to 25 MHz and with an external oscillator up to 50 MHz.
• Two power saving modes, Idle mode and Power-down mode.
• Peripheral clock scaling and individual enable/disable of peripheral functions for
additional power optimization.
• Processor wake-up from Power-down mode via external interrupt or CAN controllers.
• Dual power supply:
– CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 8.3 %).
– I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
3.2 Enhanced features
• Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original
device. They also allow for a port pin to be read at any time regardless of its function.
• Dedicated result registers for ADC reduce interrupt overhead. The ADC pads are 5 V
tolerant when configured for digital I/O function(s).
• UART0/1 include fractional baud rate generator, auto-bauding capabilities, and
handshake flow-control fully implemented in hardware.
• Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
• SPI programmable data length and master mode enhancement.
• General purpose timers can operate as external event counters.
4. Ordering options
UM10114_3
User manual
4.1 LPC2109/2119/2129
Table 2. LPC2109/2119/2129 Ordering information
Type number
Package
Name
Description
LPC2109FBD64/00 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2109FBD64/01 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2119FBD64
LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2119FBD64/00 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2119FBD64/01 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
Version
SOT314-2
SOT314-2
SOT314-2
SOT314-2
SOT314-2
Rev. 03 — 2 April 2008
© NXP B.V. 2008. All rights reserved.
5 of 386
5 Page 
NXP Semiconductors
5. Block diagram
UM10114www.DataSheet4U.com
Chapter 1: Introductory information
P0, P1
EINT3 to EINT0
4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1
n × AIN
P0[30:27], P[25:0]
P1[31:16], P1[1:0]
P2[31:0]
P3[31:0]
PWM6 to PWM1
TMS(1) TDI(1)
TRST(1) TCK(1) TDO(1)
XTAL2
XTAL1 RST
LPC21xx
LPC22xx
HIGH-SPEED
GPI/O
ARM7 local bus
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
AHB
DECODER
8/16 kB
SRAM
64/128/256 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
AHB TO APB APB
BRIDGE DIVIDER
APB (advanced
peripheral bus)
EXTERNAL MEMORY
CONTROLLER
I2C-BUS SERIAL
INTERFACE
SPI1/SSP
SERIAL INTERFACE
A/D CONVERTER
GENERAL
PURPOSE I/O
SPI0
SERIAL INTERFACE
UART0/UART1
PWM0
REAL-TIME CLOCK
CAN
SYSTEM CONTROL
WATCHDOG
TIMER
CS3 to CS0
A23 to A0
BLS3 to BLS0
OE, WE
D31 to D0
SCL
SDA
SCK1
MOSI1
MISO1
SSEL1
SCK0
MOSI0
MISO0
SSEL0
TXD0, TXD1
RXD0, RXD1
DSR1, CTS1,
DCD1, RI1
n × TD
n × RD
Grey-shaded blocks indicate configuration or pinout dependent on part and version number, see Table 1–16.
Fig 1. LPC21xx and LPC22xx block diagram
UM10114_3
User manual
Rev. 03 — 2 April 2008
© NXP B.V. 2008. All rights reserved.
11 of 386
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UM10114.PDF ] | |
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