PDF H57V1262GTR Data sheet ( Hoja de datos )

Número de pieza	H57V1262GTR
Descripción	128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History 0.1 Initial Draft 1.0 Release Draft Date Jul. 2009 Aug. 2009 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1 1 page www.DataSheet4U.com Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM CLK CKE CS RAS CAS WE U/LDQM Self refresh logic & timer Internal Row Counter Row Active Row Pre Decoder Refresh Column Active Column Pre Decoder 2Mx16 BANK 3 2Mx16 BANK 2 2Mx16 BANK 1 2Mx16 BANK 0 Memory Cell Array Y-Decoder DQ0 DQ15 Bank Select Column Add Counter A0 Address A1 Register Burst Counter Pipe Line A11 BA1 Mode Register CAS Latency Data Out Control Control BA0 Rev. 1.0 / Aug. 2009 5 5 Page www.DataSheet4U.com Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Speed (MHz) RAS Cycle Time RAS Cycle Time RAS to CAS Delay Operation Auto Refresh tRC tRRC tRCD RAS Active Time tRAS RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command tRP tRRD tCCD tWTL tDPL 200 166 143 133 Unit Note Min Max Min Max Min Max Min Max 55 - 60 - 63 - 63 - ns 55 - 60 - 63 - 63 - ns 15 - 18 - 20 - 20 - ns 38.7 100K 42 100K 42 100K 42 120 K ns 15 - 18 - 20 - 20 - ns 10 - 12 - 14 - 15 - ns 1 - 1 - 1 - 1 - CLK 0 - 0 - 0 - 0 - CLK 2 - 2 - 2 - 2 - CLK Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CL = 3 CL = 2 Power Down Exit Time Self Refresh Exit Time Refresh Time tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF tDPL + tRP 2 - 2 - 2 - 2 - CLK 0 - 0 - 0 - 0 - CLK 2 - 2 - 2 - 2 - CLK 3 - 3 - 3 - 3 - CLK - - - - - - 2 - CLK 1 - 1 - 1 - 1 - CLK 1 - 1 - 1 - 1 - CLK 1 - 64 - 64 - 64 - 64 ms Note: 1. A new command can be given tRRC after self refresh exit. Rev. 1.0 / Aug. 2009 11 11 Page

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Número de pieza	Descripción	Fabricantes
H57V1262GTR	128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O	Hynix Semiconductor

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