PDF 48LC8M32B2 Data sheet ( Hoja de datos )

Número de pieza	48LC8M32B2
Descripción	MT48LC8M32B2
Fabricantes	Micron Technology
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SYNCHRONOUS DRAM PRELIMINARY 256Mb: x32www.DataSheet4U.com SDRAM MT48LC8M32B2 - 2 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh (15.6µs/row) • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply • Supports CAS latency of 1, 2, and 3 OPTIONS • Configuration 8 Meg x 32 (2 Meg x 32 x 4 banks) MARKING 8M32B2 • Package 86-pin TSOP (400 mil) 86-pin TSOP (400 mil) Lead-free 90-ball FBGA (8mm x 13mm) 90-ball FBGA (8mm x 13mm) Lead-free TG P F51 B51 • Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) • Operating Temperature Range Commercial (0° to +70°C) Industrial (-40°C to +85°C) NOTE: 1. Available on -7 only Part Number Example: MT48LC8M32B2TG-7 -6 -7 None IT1 KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME GRADE FREQUENCY CL = 3* -6 166 MHz 5.5ns -7 143 MHz 6.0ns *CL = CAS (READ) latency SETUP TIME 1.5ns 2ns HOLD TIME 1ns 1ns Pin Assignment (Top View) 86-Pin TSOP VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE# CAS# RAS# CS# A11 BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 VSS 85 DQ15 84 VSSQ 83 DQ14 82 DQ13 81 VDDQ 80 DQ12 79 DQ11 78 VSSQ 77 DQ10 76 DQ9 75 VDDQ 74 DQ8 73 NC 72 VSS 71 DQM1 70 NC 69 NC 68 CLK 67 CKE 66 A9 65 A8 64 A7 63 A6 62 A5 61 A4 60 A3 59 DQM3 58 VSS 57 NC 56 DQ31 55 VDDQ 54 DQ30 53 DQ29 52 VSSQ 51 DQ28 50 DQ27 49 VDDQ 48 DQ26 47 DQ25 46 VSSQ 45 DQ24 44 VSS Note: The # symbol indicates signal is active LOW. Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 8 Meg x 32 2 Meg x 32 x 4 banks 4K 4K (A0–A11) 4 (BA0, BA1) 512 (A0–A8) 09005aef80cd8e48 256MbSDRAMx32.p65 – Rev. B; Pub. 03/04 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 1 page FUNCTIONAL BLOCK DIAGRAM 8 Meg x 32 SDRAM PRELIMINARY 256Mb: x32www.DataSheet4U.com SDRAM CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 BANK0 MODE REGISTER 12 A0–A11, BA0, BA1 14 ADDRESS REGISTER REFRESH 12 COUNTER 12 ROW- ADDRESS MUX 12 BANK0 ROW- ADDRESS LATCH & DECODER 4096 BANK0 MEMORY ARRAY (4,096 x 512 x 32) SENSE AMPLIFIERS 4,096 2 BANK CONTROL LOGIC 2 COLUMN- ADDRESS 9 89 COUNTER/ LATCH I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 512 (x32) COLUMN DECODER 44 DATA 32 OUTPUT REGISTER DATA 32 INPUT REGISTER 32 DQM0– DQM3 DQ0– DQ31 09005aef80cd8e48 256MbSDRAMx32.p65 – Rev. B; Pub. 03/04 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. 5 Page CAS Latency The CAS latency is the delay, in clock cycles, be- tween the registration of a READ command and the availability of the first piece of output data. The la- tency can be set to one, two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operat- ing frequencies at which each CAS latency setting can be used. CLK COMMAND DQ Figure 2 CAS Latency T0 T1 T2 READ tLZ tAC NOP tOH DOUT CAS Latency = 1 CLK COMMAND DQ T0 T1 T2 READ NOP tLZ tAC CAS Latency = 2 NOP tOH DOUT T3 PRELIMINARY 256Mb: x32www.DataSheet4U.com SDRAM Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0–M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 2 CAS Latency SPEED -6 -7 ALLOWABLE OPERATING FREQUENCY (MHz) CAS LATENCY = 1 ≤50 ≤50 CAS LATENCY = 2 ≤100 ≤100 CAS LATENCY = 3 ≤166 ≤143 CLK COMMAND T0 READ DQ T1 T2 NOP NOP tLZ tAC CAS Latency = 3 09005aef80cd8e48 256MbSDRAMx32.p65 – Rev. B; Pub. 03/04 T3 T4 NOP tOH DOUT DON’T CARE UNDEFINED 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. 11 Page

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