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PDF EM6156K600V Data sheet ( Hoja de datos )
| Número de pieza | EM6156K600V | |
| Descripción | 256Kx16 LP SRAM | |
| Fabricantes | Eorex Corporation | |
| Logotipo |  |
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256Kx16 LP SRAM EM6156K600wVwwS.DeatraSieheset4U.com
GENERAL DESCRIPTION
The EM6156K600V is a 4,194,304-bit low power CMOS static random access memory organized as
262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS
technology. Its standby current is stable within the range of operating temperature.
The EM6156K600V is well designed for low power application, and particularly well suited for battery
back-up nonvolatile memory application.
The EM6156K600V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
FEATURES
z Fast access time: 45/55/70ns
z Low power consumption:
Operating current:
40/30/20mA (TYP.)
Standby current: -L/-LL version
20/2µA (TYP.)
z Single 2.7V ~ 3.6V power supply
z All inputs and outputs TTL compatible
z Fully static operation
z Tri-state output
z Data byte control :
LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
z Data retention voltage: 1.5V (MIN.)
z Package:
44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A17
DECODER
256Kx16
MEMORY
ARRAY
DQ0-DQ7
Lower Byte
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
UB#
I/O DATA
CURCUIT
CONTROL
CIRCUIT
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A17
Address Inputs
DQ0 – DQ17 Data Inputs/Outputs
CE# Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
LB# Lower Byte Control
UB# Upper Byte Control
Vcc Power Supply
Vss Ground
COLUMN I/O
1 DCC-SR-041003-A
1 page  
256Kx16 LP SRAM EM6156K600wVwwS.DeatraSieheset4U.com
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
Dout
Previous Data Valid
tRC
tAA
tOH
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Address
tRC
CE#
tAA
OE#
tACE
Dout
LB#, UB#
High-Z
tOLZ
tCLZ
tOE
tBLZ
tBA
tOH
tCHZ
tOHZ
Valid Data
tBHZ
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
5 DCC-SR-041003-A
5 Page 
256Kx16 LP SRAM EM6156K600wVwwS.DeatraSieheset4U.com
Product ID Information
EM 61 56K 6 0 0 V T A – 45 IF*
SRAM
Family
61: Standard
Option
Configuration: Option
Version
Speed:
45ns
8: x8
16: x16
Voltage:
V: 3V
55ns
70ns
Address Density
EOREX
56K: 256K
Manufactured
Memory
W: 2.7V
~5.5V
T: 5V Package:
S: sTSOP
P: PDIP
F: SOP
B: TFBGA
T: TSOP
TEMP:
Blank: Normal
I: Industrial
Pb-Free PKG:
Blank: Normal
F: Pb-free
* Product ID example
11 DCC-SR-041003-A
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet EM6156K600V.PDF ] | |
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