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부품번호 | EDS2532CABJ 기능 |
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기능 | 256M bits SDRAM | ||
제조업체 | Elpida Memory | ||
로고 | |||
DATA SHEET
www.DataSheet4U.com
256M bits SDRAM
EDS2532CABJ (8M words × 32 bits)
Specifications
• Density: 256M bits
• Organization
⎯ 2M words × 32 bits × 4 banks
• Package: 90-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Clock frequency: 133MHz/100MHz (max.)
• 2KB page size
⎯ Row address: A0 to A11
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0460E40 (Ver. 4.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2004-2005
EDS2532CABJ
www.DataSheet4U.com
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
VT
VDD
IOS
PD
TA
Tstg
–0.5 to +3.6
–0.5 to +3.6
50
1.0
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
2.3
2.7
VSS, VSSQ
0
0
Input high voltage
VIH 1.7
VDD + 0.3
Input low voltage
VIL –0.3
0.7
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0460E40 (Ver. 4.0)
4
4페이지 EDS2532CABJ
www.DataSheet4U.com
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-75 -1A
Parameter
Symbol
min.
max.
min.
max.
Unit
System clock cycle time
(CL = 2)
tCK
10
—
10
—
ns
(CL = 3)
tCK 7.5 — 10 — ns
CLK high pulse width
tCH 2.5 —
3
— ns
CLK low pulse width
tCL 2.5 — 3
— ns
Access time from CLK
tAC —
5.4 —
6
ns
Data-out hold time
tOH 2.0 —
2.0 —
ns
CLK to Data-out low impedance tLZ
0
—0
— ns
CLK to Data-out high impedance tHZ
—
5.4 —
6
ns
Input setup time
tSI
1.5 —
2
— ns
Input hold time
tHI
0.8 —
1
— ns
Ref/Active to Ref/Active
command period
tRC
67.5 —
70
—
ns
Active to Precharge command
period
tRAS
45
120000
50
120000
ns
Active command to column
command (same bank)
tRCD
20
—
20
—
ns
Precharge to active command
period
tRP
20
—
20
—
ns
Write recovery or data-in to
precharge lead time
tDPL
15
—
20
—
ns
Last data into active latency
tDAL
2CLK + 20ns —
2CLK + 20ns —
Active (a) to Active (b) command
period
tRRD
15
—
20
—
ns
Transition time (rise and fall)
tT
0.5 5.0 0.5 5
ns
Refresh period
(4096 refresh cycles)
tREF
—
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.
2. Access time is measured at 1.2V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Notes
1
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
1
Data Sheet E0460E40 (Ver. 4.0)
7
7페이지 | |||
구 성 | 총 48 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |