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부품번호 | EDS2532EESL-75 기능 |
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기능 | 256M bits SDRAM | ||
제조업체 | Elpida Memory | ||
로고 | |||
DATA SHEET
www.DataSheet4U.com
256M bits SDRAM
EDS2532EESL-75 (8M words × 32 bits)
Specifications
• Density: 256M bits
• Organization
2M words × 32 bits × 4 banks
• Package: 92-ball FBGA
Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Clock frequency: 133MHz (max.)
• 2KB page size
Row address: A0 to A11
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Driver strength: half/quarter
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
• Operating ambient temperature range
TA = 0°C to +70°C
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
Pin Configurations
/xxx indicates active low signal.
92-ball FBGA
1 2 3 4 5 6 7 8 9 10 11
A
NC VDD VSS
B
VSSQ DQ15
C
VDDQ DQ13 DQ14
D
DQ11 DQ12
E
DQ9 DQ10 VSSQ
F
DQ8 VDDQ
G
CLK DQM1 VSS
H
CKE /CS
J
A8 NC A9
K
NC A6 A7
L
A5 A4
M
A3 DQM3 VSS
N
DQ31 VDDQ
P
DQ30 DQ29 VSSQ
R
DQ28 DQ27
S
VDDQ DQ26 DQ25
T
VSSQ DQ24
U
NC VDD VSS
(Top view)
VSS VDD NC
DQ0 VDDQ
DQ1 DQ2 VSSQ
DQ3 DQ4
VDDQ DQ5 DQ6
VSSQ DQ7
VDD DQM0 /WE
/CAS /RAS
BA0 A11 NC
A10 BA1 NC
A1 A0
VDD DQM2 A2
VSSQ DQ16
VDDQ DQ18 DQ17
DQ20 DQ19
DQ22 DQ21 VSSQ
DQ23 VDDQ
VSS VDD NC
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0888E10 (Ver. 1.0) This product became EOL in September, 2007.
Date Published March 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
EDS2532EESL-75
www.DataSheet4U.com
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
VT
VDD
IOS
PD
TA
Tstg
–0.5 to VDD +0.3 (≤ 2.4 max.)
–0.5 to +2.4
50
1.0
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
1.7
1.9
VSS, VSSQ
0
0
Input high voltage
VIH
0.8 × VDD
VDD + 0.3
Input low voltage
VIL –0.3
0.3
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. The peak of VIH = VDD + 0.5V (pulse width at VIH (max.) ≤ 3ns).
4. The bottom of VIL = VSS – 1.0V (pulse width at VIL (min.) ≤ 3ns).
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0888E10 (Ver. 1.0)
4
4페이지 EDS2532EESL-75
www.DataSheet4U.com
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-75
Parameter
Symbol min.
max.
Unit Notes
System clock cycle time
(CL = 2)
(CL = 3)
tCK 10
tCK 7.5
—
—
ns 1
ns 1
CLK high pulse width
tCH 2.5
—
ns 1, 5
CLK low pulse width
tCL 2.5
—
ns 1, 5
Access time from CLK
tAC —
6.0 ns 1, 2, 5, 6
Data-out hold time
tOH 2.5
—
ns 1, 2, 5, 6
CLK to Data-out low impedance
tLZ 0
— ns 1, 2, 3, 5, 6
CLK to Data-out high impedance
tHZ —
6.0 ns 1, 4, 6
Input setup time
tSI 1.5
—
ns 1, 5
Input hold time
tHI 0.8
—
ns 1, 5
Ref/Active to Ref/Active command period
tRC 67.5
—
ns 1
Active to Precharge command period
tRAS
45
120000
ns
1
Active command to column command (same bank) tRCD
20
—
ns 1
Precharge to active command period
tRP 20 — ns 1
Write recovery or data-in to precharge lead time
tDPL
15
—
ns 1
Last data into active latency
tDAL
2CLK + 20ns —
Active (a) to Active (b) command period
tRRD
15
—
ns 1
Transition time (rise and fall)
tT 0.5 1.0 ns
Refresh period
(4096 refresh cycles)
tREF
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5 × VDDQ.
2. Access time is measured at 0.5 × VDDQ. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
5. If tT ≥ 1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
6. Driver strength is Half condition.
Data Sheet E0888E10 (Ver. 1.0)
7
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부품번호 | 상세설명 및 기능 | 제조사 |
EDS2532EESL-75 | 256M bits SDRAM | Elpida Memory |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |