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EDS2532EGBH-TT 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EDS2532EGBH-TT은 전자 산업 및 응용 분야에서
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부품번호 EDS2532EGBH-TT 기능
기능 256M bits SDRAM WTR
제조업체 Elpida Memory
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EDS2532EGBH-TT 데이터시트, 핀배열, 회로
PRELIMINARY DATA SHEET
www.DataSheet4U.com
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2532EGBH-TT (8M words × 32 bits)
Specifications
Density: 256M bits
Organization
2M words × 32 bits × 4 banks
Package: 90-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Clock frequency: 166MHz/133MHz (max.)
2KB page size
Row address: A0 to A11
Column address: A0 to A8
Four internal banks for concurrent operation
Interface: LVCMOS
Burst lengths (BL): 1, 2, 4, 8, full page
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
/CAS Latency (CL): 3
Precharge: auto precharge option for each burst
access
Driver strength: normal, 1/2, 1/4, 1/8
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
Operating ambient temperature range
TA = –20°C to +85°C
Features
• ×32 organization
Single pulsed /RAS
Burst read/write operation and burst read/single write
operation capability
Byte control by DQM
Wide temperature range
TA = 20°C to +85°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E1200E40 (Ver. 4.0)
Date Published December 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008




EDS2532EGBH-TT pdf, 반도체, 판매, 대치품
EDS2532EGBH-TT
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Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
VT
VDD
IOS
PD
TA
Tstg
–0.5 to +2.3
–0.5 to +2.3
50
1.0
–20 to +85
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = –20°C to +85°C)
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
1.7
1.9
VSS, VSSQ
0
0
Input high voltage
VIH
0.8 × VDD
VDD + 0.3
Input low voltage
VIL –0.3
0.3
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. The peak of VIH = VDD + 0.5V (pulse width at VIH (max.) 3ns).
4. The bottom of VIL = VSS – 1.0V (pulse width at VIL (min.) 3ns).
Unit
V
V
V
V
Notes
1
2
3
4
Preliminary Data Sheet E1200E40 (Ver. 4.0)
4

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EDS2532EGBH-TT 전자부품, 판매, 대치품
EDS2532EGBH-TT
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AC Characteristics (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-6D -7B
Parameter
Symbol min.
max.
min.
max.
Unit Notes
System clock cycle time
tCK 6
— 7.5 — ns 1
CLK high pulse width
tCH 2.5
2.5 —
ns 1, 5
CLK low pulse width
tCL 2.5 —
2.5 —
ns 1, 5
Access time from CLK
tAC —
5.4 —
5.4 ns 1, 2, 5
Data-out hold time
tOH 2.5
2.5 —
ns 1, 2, 5
CLK to Data-out low impedance
tLZ 0
—0
— ns 1, 2, 3, 5
CLK to Data-out high impedance
tHZ —
5.4 —
5.4 ns 1, 4
Input setup time
tSI 1.5 — 1.5 — ns 1, 5
Input hold time
tHI 0.8 — 0.8 — ns 1, 5
Ref/Active to Ref/Active command period
tRC 60
66
ns 1
Active to Precharge command period
Active command to column command
(same bank)
tRAS
tRCD
42
18
120000
42
22.5
120000
ns
ns
1
1
Precharge to active command period
Write recovery or data-in to precharge
lead time
Last data into active latency
Active (a) to Active (b) command period
tRP
tDPL
tDAL
tRRD
18
15
2CLK +
tRP
12
22.5
15
2CLK +
tRP
15
ns 1
ns 1
ns 1
Transition time (rise and fall)
tT 0.5 1.0 0.5 1.0 ns
Refresh period
(4096 refresh cycles)
tREF
64
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5 × VDDQ.
2. Access time is measured at 0.5 × VDDQ. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
5. If tT 1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
Preliminary Data Sheet E1200E40 (Ver. 4.0)
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부품번호상세설명 및 기능제조사
EDS2532EGBH-TT

256M bits SDRAM WTR

Elpida Memory
Elpida Memory

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