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AD9961 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9961은 전자 산업 및 응용 분야에서
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부품번호 AD9961 기능
기능 (AD9961 / AD9963) Broadband MxFE
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AD9961 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Dual 10-bit/12-bit, 100 MSPS ADC
SNR = 67 dB, fIN = 30.1 MHz
Dual 10-bit/12-bit, 170 MSPS DAC
ACLR = 74 dBc
5 channels of analog auxiliary input/output
Low power, <425 mW at maximum sample rates
Supports full and half-duplex data interfaces
Small 72-lead LFCSP lead-free package
APPLICATIONS
Wireless infrastructure
Picocell, femtocell basestations
Medical instrumentation
Ultrasound AFE
Portable instrumentation
Signal generators, signal analyzers
GENERAL DESCRIPTION
The AD9961/AD9963 are pin-compatible, 10-/12-bit, low
power MxFE® converters that provide two ADC channels with
sample rates of 100 MSPS and two DAC channels with sample
rates to 170 MSPS. These converters are optimized for transmit
and receive signal paths of communication systems requiring low
power and low cost. The digital interfaces provide flexible
clocking options. The transmit is configurable for 1×, 2×, 4×,
and 8× interpolation. The receive path has a bypassable 2×
decimating low-pass filter.
The AD9961 and AD9963 have five auxiliary analog channels.
Three are inputs to a 12-bit ADC. Two of these inputs can be
configured as outputs by enabling 10-bit DACs. The other
two channels are dedicated outputs from two independent
12-bit DACs.
The high level of integrated functionality, small size, and low
power dissipation of the AD9961/AD9963 make them well-
suited for portable and low power applications.
10-/12-Bit,
Low Power, Broadband MxFE
AD9961/AD9963
FUNCTIONAL BLOCK DIAGRAM
AD9961/AD9963
TEMPERATURE
SENSOR
DLLFILT
CLKP
CLKN
DLL AND
CLOCK
DISTRIBUTION
AUX
ADC
AUX
DAC
AUX
DAC
MUX
AUXIN1
AUXIO2
AUXIO3
TXCLK
TXIQ/TXnRX
TXD[11:0]
TRXCLK
TRXIQ
TRXD[11:0]
RESET
SDIO
SCLK
CS
INTERNAL
DATA
ASSEMBLER
LPF
1/2/4/8
LPF
1/2/4/8
LPF
1/2
LPF
1/2
SERIAL
PORT
LOGIC
REFERENCES
AND BIAS
12-BIT
DAC
12-BIT
DAC
12-BIT
ADC
12-BIT
ADC
AUX
DAC
AUX
DAC
LDO
VREGs
TXIP
TXIN
TXQP
TXQN
RXIP
RXIN
RXQP
RXQN
DAC12A
DAC12B
Figure 1.
PRODUCT HIGHLIGHTS
1. High Performance with Low Power Consumption.
The DACs operate on a single 1.8 V to 3.3 V supply.
Transmit path power consumption is <100 mW at
170 MSPS. Receive path power consumption is <350 mW
at 100 MSPS from 1.8 V supply. Sleep and power-down
modes are provided for low power idle periods.
2. High Integration.
The dual transmit and dual receive data converters, five
channels of auxiliary data conversion and clock generation
offer complete solutions for many modem designs.
3. Flexible Digital Interface.
The interface mates seamlessly to most digital baseband
processors.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.




AD9961 pdf, 반도체, 판매, 대치품
AD9961/AD9963
Data Sheet
TMIN to TMAX, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, ADC sample rate = 100 MSPS. No
decimation, unless otherwise noted.
Table 2. Rx Path Specifications
Parameter
Rx ADC DC CHARACTERISTICS
Resolution
Differential Nonlinearity
Gain Error
Offset Error
Input Voltage Range
Input Capacitance
Rx ADC AC SPECIFICATIONS
Maximum Sample Rate
Spurious Free Dynamic Range
fIN = 10.1 MHz
fIN = 70.1 MHz
Two-Tone Intermodulation Distortion
fIN1 = 10 MHz, fIN2 = 11 MHz
fIN1 = 29 MHz, fIN2 = 32 MHz
Signal-to-Noise Ratio
fIN = 10.1 MHz
fIN = 30.1 MHz
fIN = 70.1 MHz
RXCML OUTPUTS
Output Voltage
Output Current
Rx DIGITAL FILTER CHARACTERISTICS
2× Decimation
Latency (ADC Clock Cycles)
Passband Ripple; fOUT/fDAC (0.4 × fDATA)
Stop-Band Rejection (fDATA ± 0.4 × fDATA)
AD9961
AD9963
Min Typ
Max Min Typ
Max Unit
10 12 Bits
0.1 0.3 LSB
±1 ±1 %FSR
±0.5 ±0.5 %FSR
1.56 1.56 V p-p diff
8 8 pF
100 100 MSPS
77 77 dBc
75 73 dBc
78 82 dBc
76 80 dBc
61 68 dBFS
60 67 dBFS
60 66 dBFS
1.4
0.1
1.4 V
0.1 mA
49 49 Cycles
0.2 0.2 fOUT/fDAC
70 70 dB
Rev. A | Page 4 of 60

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AD9961 전자부품, 판매, 대치품
Data Sheet
Table 5. Digital Logic Level Specifications
Parameter
CMOS INPUT LOGIC LEVEL
VIN Logic High
VIN Logic High
VIN Logic High
VIN Logic Low
VIN Logic Low
VIN Logic Low
CMOS OUTPUT LOGIC LEVEL
VOUT Logic High
VOUT Logic High
VOUT Logic High
VOUT Logic Low
VOUT Logic Low
VOUT Logic Low
DAC CLOCK INPUT
Differential Peak-to-Peak Voltage
Duty Cycle
Slew Rate
DIRECT CLOCKING
Clock Rate
DLL ENABLED
Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate
Minimum Pulse Width High (tHIGH)
Minimum Pulse Width Low (tLOW)
Setup Time, SDIO (Data In) to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDIO (Data Out) to SCLK (tDV)
Setup Time, CS to SCLK (tS)
AD9961/AD9963
Conditions
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
CLKP/CLKN inputs
DLL delay line output
Min Typ Max
Unit
1.2 V
1.7 V
2.0 V
0.5 V
0.7 V
0.8 V
1.35 V
2.05 V
2.4 V
0.4 V
0.4 V
0.4 V
200 400 CLK33V mV p-p diff
45 55 %
0.1 V/ns
0.1 200 MHz
%
100 310 MHz
50 MHz
10 ns
10 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
Rev. A | Page 7 of 60

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