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WED3DG6466V-D2 데이터시트 PDF




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기능 SDRAM UNBUFFERED
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WED3DG6466V-D2 데이터시트, 핀배열, 회로
White Electronic Designs
WED3DG6466V-D2
512MB – 64Mx64, SDRAM UNBUFFERED
FEATURES
DESCRIPTION
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM components
in TSOP II package and one 2K EEPROM in an 8 Pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 Pin DIMM multilayer FR4 Substrate.
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available with "WP" Write Protect on Pin 81 option
• WED3DG6366V-D2
3.3V ± 0.3V Power Supply
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• Lead-Free or RoHS Products
• Vendor source control options
• Industrial temperature option
168 Pin DIMM JEDEC
• PCB: 30.48 (1.20") MAX
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin Front Pin
1 VSS 29
2 DQ0 30
3 DQ1 31
4 DQ2 32
5 DQ3 33
6 VDD 34
7 DQ4 35
8 DQ5 36
9 DQ6 37
10 DQ7 38
11 DQ8 39
12 VSS 40
13 DQ9 41
14 DQ10 42
15 DQ11 43
16 DQ12 44
17 DQ13 45
18 VDD 46
19 DQ14 47
20 DQ15 48
21 *CBO 49
22 *CB1 50
23 Vss 51
24 NC 52
25 NC 53
26 VDD 54
27 WE# 55
28 DQM0 56
Front
DQM1
CS0#
DNU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
VSS
DNU
CS2#
DQM2
DQM3
DNU
VDD
NC
NC
*CB2
*CB3
VSS
DQ16
DQ17
Pin Front Pin Back Pin Back Pin Back
57 DQ18 85 VSS 113 DQM5 141 DQ50
58 DQ19 86 DQ32 114 *CS1# 142 DQ51
59 VDD 87 DQ33 115 RAS# 143 VDD
60 DQ20 88 DQ34 116 VSS
144 DQ52
61 NC 89 DQ35 117 A1 145 NC
62 *VREF 90
NC 118 A3
146 *VREF
63 *CKE1 91 DQ36 119 A5
147 DNU
64 VSS 92 DQ37 120 A7 148 VSS
65 DQ21 93 DQ38 121 A9
149 DQ53
66 DQ22 94 DQ39 122 BA0 150 DQ54
67 DQ23 95 DQ40 123 A11 151 DQ55
68 VSS 96 VSS 124 VDD 152 VSS
69 DQ24 97 DQ41 125 *CK1 153 DQ56
70 DQ25 98 DQ42 126 A12 154 DQ57
71 DQ26 99 DQ43 127 VSS
155 DQ58
72 DQ27 100 DQ44 128 CKE0 156 DQ59
73 VDD 101 DQ45 129 CS3# 157 VDD
74 DQ28 102 VDD 130 DQM6 158 DQ60
75 DQ29 103 DQ46 131 DQM7 159 DQ61
76 DQ30 104 DQ47 132 *A13 160 DQ62
77 DQ31 105 *CB4 133 VDD 161 DQ63
78 VSS 106 *CB5 134 NC 162 VSS
79 CK2 107 VSS 135 NC
163 *CK3
80 NC 108 NC 136 *CB6 164 NC
81 ***WP 109 NC 137 *CB7 165 **SA0
82 **SDA 110 VDD 138 VSS
166 **SA1
83 **SCL 111 CAS# 139 DQ48 167 **SA2
84 VDD 112 DQM4 140 DQ49 168 VDD
A0 - A12
BA0-1
DQ0-63
CBO-7
CK0,CK2
CKE0#
CS0# - CS2#
RAS#
CAS#
WE#
DQM0-7
VDD
VSS
SDA
SCL
DNU
NC
WP
Address input (Multiplexed)
Select Bank
Data Input/Output
Check bit (Data-in/Data-out)
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Serial data I/O
Serial clock
Do not use
No Connect
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which does not
support SPD.
*** WP available on the WED3DG6364V-D2 only
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
www.DataSheet.in
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WED3DG6466V-D2 pdf, 반도체, 판매, 대치품
White Electronic Designs
WED3DG6466V-D2
IDD SPECIFICATIONS AND CONDITIONS
VCC, VCCQ = +3.3V ±0.3V; SDRAM component values only
MAX
PARAMETER/CONDITION
SYMBOL
7
7.5 & 10
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN)
STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active
after tRCD met; No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device
banks active
AUTO REFRESH CURRENT
tRFC = tRFC (MIN)
CKE = HIGH; CS# = HIGH
tRFC = 7.8125µs
SELF REFRESH CURRENT: CKE < 0.2V
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
1,600
56
720
1,440
50
280
1,600
1,360
2,640
2,480
96 96
60
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
UNITS
mA
mA
mA
mA
mA
mA
mA
NOTES
1
1
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
www.DataSheet.in
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WED3DG6466V-D2 전자부품, 판매, 대치품
White Electronic Designs
WED3DG6466V-D2
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased
at 1.4V; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.)
The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount
of frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5.
22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL
(MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC133, PC100 specify three clocks.
27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
www.DataSheet.in
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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