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PDF 24WC05J Data sheet ( Hoja de datos )
| Número de pieza | 24WC05J | |
| Descripción | CAT24WC05J | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24WC03/05
2K/4K-Bit Serial EEPROM with Partial Array Write Protection
FEATURES
s Self-timed write cycle with auto-clear
s 400 kHz I2C bus compatible*
s 1,000,000 Program/Erase cycles
s 1.8 to 5.5 volt operation
s Low power CMOS technology
s Write protect feature
–Top 1/2 array protected when WP at VIH
rtss 16-Byte page write buffer
DESCRIPTION
aThe CAT24WC03/05 is a 2K/4K-bit Serial CMOS
EEPROM internally organized as 256/512 words of 8
Pbits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
s 100 Year data retention
s 8-pin DIP, 8-pin SOIC, 8-lead MSOP and 8-pin
TSSOP Package
s Commercial, industrial and automotive
temperature ranges
s "Green" package options available
CAT24WC03/05 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface, has
a special write protection feature, and is available in 8-
pin DIP or 8-pin SOIC packages.
dPIN CONFIGURATION
DIP Package (P, L, GL)
SOIC Package (J, W, GW)
BLOCK DIAGRAM
EXTERNAL LOAD
eA0
uA1
A2
tinVSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
VCC
VSS
MSOP Package (R, Z, GZ)
TSSOP Package (U, Y, GY)
A0
nA1
A2
VSS
1
2
3
4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8
SDA
VCC
7 WP
6 SCL
5 SDA
o WP
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
cPIN FUNCTIONS
isPin Name
Function
DA0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
Serial Data/Address
HIGH VOLTAGE/
SCL Serial Clock
TIMING CONTROL
WP Write Protect
VCC +1.8V to +5.5V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1005, Rev. F
www.DataSheet.in
1 page  
CAT24WC03/05
A total of four devices can be addressed on a single bus
when using the CAT24WC05 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to VSS or left
floating. If only one CAT24WC05 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to VSS.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
WP: Write Protect
The bus Master begins a transmission by sending a
If the WP pin is tied to VCC the upper half of memory array START condition. The Master then sends the address
becomes Write Protected (READ only)(locations 80H to
FFH for the CAT24WC03 and locations 100H to 1FFH
for the CAT24WC05). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
rtsI2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
a(1) Data transfer may be initiated only when the bus is
not busy.
P(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
dinterpreted as a START or STOP condition.
eSTART Condition
The START Condition precedes all commands to the
udevice, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05 monitor
the SDA and SCL lines and will not respond until this
tincondition is met.
Figure 4. Acknowledge Timing
SCL FROM
nMASTER
1
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05 (see Fig. 5). The next
three significant bits (A2, A1, A0) are the device address
bits and define which device or which part of the device
the Master is accessing. Up to eight CAT24WC03 and
four CAT24WC05 can be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC03/05 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
89
oDATA OUTPUT
FROM TRANSMITTER
iscDATA OUTPUT
FROM RECEIVER
D START
ACKNOWLEDGE
Figure 5. Slave Address Bits
24WC03 1 0 1 0 A2 A1 A0 R/W
24WC05 1 0 1 0 A2 A1 a8 R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8 corresponds to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
www.DataSheet.in
5
Doc. No. 1005, Rev. F
5 Page 
8-LEAD TSSOP (U, Y, GY)
CAT24WC03/05
Discontinued Parts
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
www.DataSheet.in
11
Doc. No. 1005, Rev. F
11 Page | ||
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| PDF Descargar | [ Datasheet 24WC05J.PDF ] | |
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