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부품번호 | NLX1G125 기능 |
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기능 | Non-Inverting 3-State Buffer | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 7 페이지수
NLX1G125
Non-Inverting 3-State Buffer
The NLX1G125 is an advanced high−speed 2−input CMOS
non−inverting 3−state buffer in ultra−small footprint.
The NLX1G125 input structures provide protection when voltages
up to 7.0 V are applied, regardless of the supply voltage.
Features
• High Speed: tPD = 2.7 ns (Typ) @ VCC = 5.0 V
• Designed for 1.65 V to 5.5 V VCC Operation
• Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
• 24 mA Balanced Output Source and Sink Capability
• Balanced Propagation Delays
• Overvoltage Tolerant (OVT) Input Pins
• Ultra−Small Packages
• These are Pb−Free Devices
OE 1
IN A 2
GND
3
5 VCC
4 OUT Y
Figure 1. Pinout (Top View)
OE EN
IN A
OUT Y
Figure 2. Logic Symbol
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MARKING
DIAGRAM
5 PIN FLIP−CHIP
CASE 499BG
XXXX
AYWW
A1
XXXX
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENT
1 OE
2 IN A
3 GND
4 OUT Y
5 VCC
FUNCTION TABLE
A Input
OE Input
Y Output
LL
HL
XH
L
H
Z
X = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. P0
www.DataSheet.in
1
Publication Order Number:
NLX1G125/D
NLX1G125
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 2.5 ns)
Symbol
Parameter
VCC
(V)
Test
Condition
TA = 25 5C
Min Typ Max
TA = −555C to
+1255C
Min Max
Unit
tPLH,
tPHL
Propagation Delay,
Input to Output
(Figures 3 and 4,
Table 1)
tPZH,
tPZL
Output Enable Time
(Figures 5, 6and 7,
Table 1)
1.65−1.95 RL = 1 MW, CL = 15 pF
2.0
6.0
10
2.0 10.5 ns
2.3−2.7 RL = 1 MW, CL = 15 pF 1.0 3.4 7.5 1.0 8.0
3.0−3.6 RL = 1 MW, CL = 15 pF 0.8 2.5 5.2 0.8 5.5
RL = 500 W, CL = 50 pF
1.2
3.1
5.7
1.2
6.0
4.5−5.5 RL = 1 MW, CL = 15 pF 0.5 1.8 4.5 0.5 4.8
RL = 500 W, CL = 50 pF
0.8
2.3
5.0
0.8
5.3
1.65−1.95 RL = 250 W, CL = 50 pF
2.0
7.6
9.5
2.0
10
ns
2.3−2.7
1.8 8.5 1.8 9.0
3.0−3.6
1.2 6.2 1.2 6.5
4.5−5.5
0.8 5.5 0.8 5.8
tPHZ,
tPLZ
Output Disable Time
(Figures 5, 6and 7,
Table 1)
1.65−1.95
2.3−2.7
3.0−3.6
RL
=CLR=1
= 5−0
50 pF
W,
2.0 8.0 10 2.0 10.5 ns
1.5 8.0 1.5 8.5
0.8 5.7 0.8 6.0
4.5−5.5
0.3 4.7 0.3 5.0
CIN Input Capacitance
5.5 VIN = 0 V or VCC
2.5
pF
COUT
Output Capacitance
5.5
VIN = 0 V or VCC
2.5
pF
CPD Power Dissipation
Capacitance (Note 7)
3.3
5.5
10 MHz
VIN = 0 V or VCC
9.0
11
pF
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without
load. Average operating current can be obtained
dynamic power consumption: PD = CPD • VCC2 •
by
fin
the equation
+ ICC • VCC.
ICC(OPR)
=
CPD
•
VCC
•
fin
+
ICC.
CPD
is
used
to
determine
the
no−load
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4
4페이지 NLX1G125
PACKAGE DIMENSIONS
5 PIN FLIP−CHIP
CASE 499BG−01
ISSUE O
PIN A1
REFERENCE
4X
DÈÈÈÈ
0.10 C
AB
E
0.10 C
TOP VIEW
A1
A
0.05 C
SIDE VIEW
C
SEATING
PLANE
5X b
0.05 C A B
0.03 C
e
C
B
A
12
e/2
e
e
BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A 0.44 0.50
A1 0.15 0.19
b 0.21 0.25
D 0.90 BSC
E 1.40 BSC
e 0.50 BSC
SOLDERING FOOTPRINT*
0.50 PITCH
0.50 PITCH
A1
5X 0.25
PACKAGE
OUTLINE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NL17SZ125/D
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부품번호 | 상세설명 및 기능 | 제조사 |
NLX1G125 | Non-Inverting 3-State Buffer | ON Semiconductor |
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