|
|
|
부품번호 | C8051T605 기능 |
|
|
기능 | (C8051T601 - C8051T606) Mixed-Signal Byte-Programmable EPROM MCU | ||
제조업체 | Silicon Laboratories | ||
로고 | |||
전체 30 페이지수
C8051T600/1/2/3/4/5/6
Mixed-Signal Byte-Programmable EPROM MCU
Analog Peripherals
- 10-Bit ADC (‘T600/602/604 only)
• Up to 500 ksps
• Up to 8 external inputs
• VREF external pin, Internal Regulator or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current
On-Chip Debug
- C8051F300 can be used as code development
platform; complete development kit available
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
- Provides breakpoints, single stepping,
inspect/modify memory and registers
Supply Voltage 1.8 to 3.6 V
- On-chip LDO for internal core supply
- Built-in voltage supply monitor
Temperature Range: –40 to +85 °C
Package Options:
- 3 x 3 mm QFN11
- 2 x 2 mm QFN10 (C8051T606 Only)
- MSOP10 (C8051T606 Only)
- SOIC14 (C8051T600/1/2/3/4/5 Only)
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 or 128 Bytes internal data RAM
- 8, 4, 2, or 1.5 kB byte-programmable EPROM code
memory
Digital Peripherals
- Up to 8 Port I/O with high sink current capability
- Hardware enhanced UART and SMBus™ serial
ports
- Three general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
• 8 or 16-bit PWM
• Rising / falling edge capture
• Frequency output
• Software timer
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
- External oscillator: RC, C, or CMOS Clock
- Can switch between clock sources on-the-fly; useful
in power saving modes
ANALOG
PERIPHERALS
A 10-bit
M
U
500ksps
X ADC
TEMP
SENSOR
+
C8051T600/2/4
-
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
CALIBRATED PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
1.5/2/4/8kB
EPROM
12
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
128/256 B
SRAM
POR WDT
Rev. 1.2 3/09
Copyright © 2009 by Silicon Laboratories
C8051T600/1/2/3/4/5/6
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
www.DataSheet.in
C8051T600/1/2/3/4/5/6
23.3.2. Arbitration.............................................................................................. 122
23.3.3. Clock Low Extension............................................................................. 122
23.3.4. SCL Low Timeout.................................................................................. 122
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 123
23.4. Using the SMBus........................................................................................... 123
23.4.1. SMBus Configuration Register.............................................................. 123
23.4.2. SMB0CN Control Register .................................................................... 127
23.4.3. Data Register ........................................................................................ 130
23.5. SMBus Transfer Modes................................................................................. 131
23.5.1. Write Sequence (Master) ...................................................................... 131
23.5.2. Read Sequence (Master) ...................................................................... 132
23.5.3. Write Sequence (Slave) ........................................................................ 133
23.5.4. Read Sequence (Slave) ........................................................................ 134
23.6. SMBus Status Decoding................................................................................ 134
24. UART0 ................................................................................................................... 137
24.1. Enhanced Baud Rate Generation.................................................................. 138
24.2. Operational Modes ........................................................................................ 139
24.2.1. 8-Bit UART ............................................................................................ 139
24.2.2. 9-Bit UART ............................................................................................ 140
24.3. Multiprocessor Communications ................................................................... 141
25. Timers ................................................................................................................... 145
25.1. Timer 0 and Timer 1 ...................................................................................... 147
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 147
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 148
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 149
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 150
25.2. Timer 2 .......................................................................................................... 155
25.2.1. 16-bit Timer with Auto-Reload............................................................... 155
25.2.2. 8-bit Timers with Auto-Reload............................................................... 156
26. Programmable Counter Array............................................................................. 160
26.1. PCA Counter/Timer ....................................................................................... 161
26.2. PCA0 Interrupt Sources................................................................................. 162
26.3. Capture/Compare Modules ........................................................................... 163
26.3.1. Edge-triggered Capture Mode............................................................... 164
26.3.2. Software Timer (Compare) Mode.......................................................... 165
26.3.3. High-Speed Output Mode ..................................................................... 166
26.3.4. Frequency Output Mode ....................................................................... 167
26.3.5. 8-bit Pulse Width Modulator Mode ....................................................... 168
26.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 169
26.4. Watchdog Timer Mode .................................................................................. 170
26.4.1. Watchdog Timer Operation ................................................................... 170
26.4.2. Watchdog Timer Usage ........................................................................ 171
26.5. Register Descriptions for PCA0..................................................................... 173
27. C2 Interface .......................................................................................................... 178
27.1. C2 Interface Registers................................................................................... 178
4
www.DataSheet.in
Rev. 1.2
4페이지 C8051T600/1/2/3/4/5/6
13. Comparator0
Figure 13.1. Comparator0 Functional Block Diagram ............................................. 59
Figure 13.2. Comparator Hysteresis Plot ................................................................ 60
Figure 13.3. Comparator Input Multiplexer Block Diagram ...................................... 63
14. CIP-51 Microcontroller
Figure 14.1. CIP-51 Block Diagram ......................................................................... 65
15. Memory Organization
Figure 15.1. Program Memory Map ......................................................................... 74
Figure 15.2. RAM Memory Map .............................................................................. 75
16. Special Function Registers
17. Interrupts
18. Power Management Modes
19. Reset Sources
Figure 19.1. Reset Sources ..................................................................................... 92
Figure 19.2. Power-On and VDD Monitor Reset Timing ......................................... 93
20. EPROM Memory
21. Oscillators and Clock Selection
Figure 21.1. Oscillator Options .............................................................................. 100
22. Port Input/Output
Figure 22.1. Port I/O Functional Block Diagram .................................................... 106
Figure 22.2. Port I/O Cell Block Diagram .............................................................. 107
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 111
Figure 22.4. Priority Crossbar Decoder Example 1 - No Skipped Pins ................. 112
Figure 22.5. Priority Crossbar Decoder Example 2 - Skipping Pins ...................... 113
23. SMBus
Figure 23.1. SMBus Block Diagram ...................................................................... 120
Figure 23.2. Typical SMBus Configuration ............................................................ 121
Figure 23.3. SMBus Transaction ........................................................................... 122
Figure 23.4. Typical SMBus SCL Generation ........................................................ 124
Figure 23.5. Typical Master Write Sequence ........................................................ 131
Figure 23.6. Typical Master Read Sequence ........................................................ 132
Figure 23.7. Typical Slave Write Sequence .......................................................... 133
Figure 23.8. Typical Slave Read Sequence .......................................................... 134
24. UART0
Figure 24.1. UART0 Block Diagram ...................................................................... 137
Figure 24.2. UART0 Baud Rate Logic ................................................................... 138
Figure 24.3. UART Interconnect Diagram ............................................................. 139
Figure 24.4. 8-Bit UART Timing Diagram .............................................................. 139
Figure 24.5. 9-Bit UART Timing Diagram .............................................................. 140
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 141
25. Timers
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 148
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 149
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 150
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 155
www.DataSheet.in
Rev. 1.2
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ C8051T605.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
C8051T600 | (C8051T600 - C8051T605) Mixed Signal OTP EPROM MCU Family | Silicon Laboratories |
C8051T601 | (C8051T601 - C8051T606) Mixed-Signal Byte-Programmable EPROM MCU | Silicon Laboratories |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |