PDF CY62136EV30 Data sheet ( Hoja de datos )

Número de pieza	CY62136EV30
Descripción	2-Mbit (128K x 16) Static RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM Features • Very high speed: 45 ns • Wide voltage range: 2.20V–3.60V • Pin-compatible with CY62136CV30 • Ultra low standby power — Typical standby current: 1µA — Maximum standby current: 7µA • Ultra-low active power — Typical active current: 2 mA @ f = 1 MHz • Easy memory expansion with CE, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II packages Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS 128K x 16 RAM Array Functional Description[1] The CY62136EV30 is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05569 Rev. B Revised January 6, 2006 www.DataSheet.in [+] Feedback 1 page CY62136EV30 MoBL® Switching Characteristics Over the Operating Range [10, 11, 12, 13] 45 ns Parameter Description Min. Max. Unit Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[13] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z[11] OE HIGH to High Z[11, 12] CE LOW to Low Z[11] CE HIGH to High Z[11, 12] CE LOW to Power-Up CE HIGH to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[11] BLE/BHE HIGH to HIGH Z[11, 12] 45 ns 45 ns 10 ns 45 ns 22 ns 5 ns 18 ns 10 ns 18 ns 0 ns 45 ns 22 ns 5 ns 18 ns tWC Write Cycle Time 45 ns tSCE CE LOW to Write End 35 ns tAW Address Set-Up to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE/BHE LOW to Write End 35 ns tSD Data Set-Up to Write End 25 ns tHD tHZWE tLZWE Data Hold from Write End WE LOW to High-Z[11, 12] WE HIGH to Low-Z[11] 0 ns 18 ns 10 ns Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05569 Rev. B www.DataSheet.in Page 5 of 12 [+] Feedback 5 Page Package Diagrams (continued) 44-pin TSOP II (51-85087) CY62136EV30 MoBL® 51-85087-A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05569 Rev. B Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. www.DataSheet.in [+] Feedback 11 Page

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Número de pieza	Descripción	Fabricantes
CY62136EV30	2-Mbit (128K x 16) Static RAM	Cypress Semiconductor

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