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PDF CY62136FV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62136FV30 | |
| Descripción | 2-Mbit (128K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62136FV30 MoBL®
2-Mbit (128K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive: –40°C to +125°C
■ Wide voltage range: 2.20V–3.60V
■ Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
■ Ultra low standby power
❐ Typical standby current: 1µA
❐ Maximum standby current: 5 µA (Industrial)
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO0 through IO15) are placed in a high impedance
state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A10
A9
A8
A7
AA65
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08402 Rev. *D
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 03, 2007
1 page  
CY62136FV30 MoBL®
Switching Characteristics
Over the Operating Range [11, 12]
Parameter
Description
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z [13]
tHZOE
OE HIGH to High Z [13, 14]
tLZCE
CE LOW to Low Z [13]
tHZCE
CE HIGH to High Z [13, 14]
tPU CE LOW to Power Up
tPD CE HIGH to Power Down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low Z [13]
tHZBE
BLE/BHE HIGH to High Z [13, 14]
Write Cycle [15]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold From Write End
WE LOW to High Z [13, 14]
WE HIGH to Low Z [13]
45 ns (Industrial)
Min Max
55 ns (Automotive)
Min Max
Unit
45 55 ns
45 55 ns
10 10 ns
45 55 ns
22 25 ns
5 5 ns
18 20 ns
10 10 ns
18 20 ns
0 0 ns
45 55 ns
22 25 ns
5 10 ns
18 20 ns
45 55 ns
35 40 ns
35 40 ns
0 0 ns
0 0 ns
35 40 ns
35 40 ns
25 25 ns
0 0 ns
18 20 ns
10 10 ns
Notes
11.
Test conditions for all parameters,
levels of 0 to VCC(typ), and output
other than tri-state parameters,
loading of the specified IOL/IOH
assume signal transition time of 3 ns
as shown in the “AC Test Loads and
(1V/ns) or less, timing
Waveforms” on page
reference
4.
levels
of
VCC(typ)/2,
input
pulse
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13.
At any given
device.
temperature
and
voltage
condition,
tHZCE
is
less
than
tLZCE,
tHZBE
is
less
than
tLZBE,
tHZOE
is
less
than
tLZOE,
and
tHZWE
is
less
than
tLZWE
for
any
given
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15.
The internal write time of the
signals can terminate a write
memory is defined by the
by going INACTIVE. The
overlap of WE, CE =
data input setup and
hVoILld,
BtimHEinganadre/orreBfeLrEen=ceVdIL.toAtlhl seigendagles
are ACTIVE
of the signal
to initiate a write and any
that terminates the write.
of
these
Document Number: 001-08402 Rev. *D
Page 5 of 12
www.DataSheet.in
5 Page 
Package Diagrams (continued)
Figure 12. 44-Pin TSOP II
CY62136FV30 MoBL®
51-85087-*A
Document Number: 001-08402 Rev. *D
www.DataSheet.in
Page 11 of 12
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