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BD3490FV 데이터시트 PDF




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기능 Sound Processors
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BD3490FV 데이터시트, 핀배열, 회로
Datasheet
Analog Audio Processors
Sound Processors with Built-in
Surround Sound Function
BD3490FV
General Description
Built in stereo 4 input selectors and volume that there is
not an impedance change of a volume terminal. And this
is sound processor can realize 2-band equalizer
(bass/treble, gain±14dB / 2dB_step) and bass-boost,
output-gain, surround by external components.
Features
„ Built in stereo 4 input selectors (single end).
„ Built-in input gain controller for volume of a portable
audio input.
„ When the volume setting exchanging, it can use a
volume input terminal as a microphone input terminal
because there is not an impedance change of a
volume input terminal.
„ Bi-CMOS process is suitable for the design of low
current and low energy. And it provides more quality
for Bi-CMOS small scale regulator and heat in a set.
„ The package of this IC is SSOP-B28. It gathers a
sound input terminals, sound output terminals
respectively and it arranges them, to be arranging
facilitates the laying-out of PCB pattern and reduces
PCB area to one-way in the flow of the signal.
Key Specifications
„ Current upon no signal:
„ Total harmonic distortion:
„ Maximum input voltage:
„ Cross-talk between selectors:
„ Volume Control range:
„ Output noise voltage:
„ Residual output noise voltage:
„ Operating Range of Temperature:
7mA(Typ.)
0.002%(Typ.)
2.4Vrms(Typ.)
100dB(Typ.)
0dB to -87dB
5μVrms(Typ.)
5μVrms(Typ.)
-40to +85
package(s)
SSOP-B28
W(Typ.) x D(Typ.) x H(Max.)
10.00mm x 7.60mm x 1.35mm
Applications
„ It is the optimal for the mini compo or micro compo.
Besides, it is possible to use for the audio equipment
of TV, DVD etc with all kinds
SSOP-B28
Typical Application Circuit
FIL GND
10μ
28
FIL
VCC/2
27
GND
SDA
26
SDA
SCL
VCC
OUT1
10μ
0.1μ
4.7μ
22k 0.0047μ
25
SCL
24
VCC
23
OUT1
22
SB1
21
SR
20
SB2
I2C BUS LOGIC
VCC
OUT2
4.7μ
0.1μ
4.7k
0.1μ
0.1μ
4.7k
0.1μ
19 18 17 16 15
OUT2
BCB1
BCA1
BCA2
BCB2
Bass
Gain=±14dB/2dB step
Treble
Gain=±14dB/2dB step
Surround
Volume
0dB~ -87dB/1dB step, -∞dB, Independent control
Input Gain
0~+8dB/2dB step 12, 16, 20dB
Surround
Gain=OFF, Low, Middle, High
TrebleBass
Input Gain
Input Selector
Volume Volume
50k
A1
1
1μ
50k
A2
2
1μ
50k
B1
3
1μ
50k
B2
4
1μ
50k
C1
5
1μ
50k
C2
6
1μ
50k
D1
7
1μ
50k
D2
8
1μ
SEL2
9
SEL1
10
VOL1
11
2.2μ
VOL2
12
2.2μ
TC2
13
TC1
14
0.0047μ 0.0047μ
A1 A2 B1 B2 C1 C2 D1 D2
Figure 1. Application Circuit Diagram
Product structureSilicon monolithic integrated circuit
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed protection against radioactive rays
1/30
TSZ02201-0V2V0E100030-1-2
2012.10.05 Rev.001




BD3490FV pdf, 반도체, 판매, 대치품
BD3490FV
Datasheet
Electrical Characteristic
(Unless specified particularly, Ta=25, VCC=9.0V, f=1kHz, Vin=1Vrms, Rg=600Ω, RL=10kΩ, A input, Input gain 0dB,
Volume 0dB, Bass 0dB, Treble 0dB, Surround off)
Limit
Item Symbol
Unit Condition
Min. Typ. Max.
Current upon no signal
IQ 7 15 mA No signal
Voltage gain
GV -1.5 0 1.5 dB Gv=20log(VOUT/VIN)
Channel balance
CB -1.5 0 1.5 dB CB = GV1-GV2
Total harmonic distortion
Output noise voltage *
Residual output noise voltage *
Cross-talk between channels *
Input impedance
THD+N
VNO1
VNO1
CTC
RIN
0.002 0.1
VOUT=1Vrms
BW=400-30KHz
5
20
μVrms
Rg = 0Ω
BW = IHF-A
5
20
μVrms
Rg = 0Ω
BW = IHF-A
-100 -80
Rg = 0Ω
dB CTC=20log(VOUT/VOUT)
BW = IHF-A
35 50 65
kΩ
Maximum input voltage
Cross-talk between selectors *
Control range
VIM
CTS
GV MAX
2.1 2.4
-
-100 -84
-90 -87 -84
Vrms
dB
dB
VIM at THD+N(VOUT)=1
BW=400-30KHz
Rg = 0Ω
CTS=20log(VOUT/VOUT)
BW = IHF-A
VIN=2Vrms
Gv=20log(VOUT/VIN)
Maximum attenuation *
Maximum boost gain
Maximum cut gain
Maximum boost gain
Maximum cut gain
GV MIN
-100 -80
GB BST 11.5 14 16.5
GB CUT -16.5 -14 -11.5
GT BST 11.5 14 16.5
GT CUT -16.5 -14 -11.5
dB
Volume = -
Gv=20log(VOUT/VIN)
Gain = 14dB, f = 100Hz
dB VIN=100mVrms
Gv=20log(VOUT/VIN)
Gain = -14dB, f = 100Hz
dB VIN=2Vrms
Gv=20log(VOUT/VIN)
Gain = 14dB, f = 100Hz
dB VIN=100mVrms
Gv=20log(VOUT/VIN)
Gain = -14dB, f = 100Hz
dB VIN=2Vrms
Gv=20log(VOUT/VIN)
VP-9690A(Average value detection, effective value display) filter by Matsushita Communication is used for measurement.
Phase between input / output is same.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/30
TSZ02201-0V2V0E100030-1-2
2012.10.05 Rev.001

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BD3490FV 전자부품, 판매, 대치품
BD3490FV
CONTROL SIGNAL SPECIFICATION
(1) Electrical specifications and timing for bus lines and I/O stages
Datasheet
SDA
SCL
tBUF
tLOW
tR
tF
tHD;STA
tSP
tHD;STA
tHD;DAT
PS
tHIGH
tSU;DAT tSU;STA Sr
Figure 12. Definition of timing on the I2C-bus
tSU;STO
P
Table 1. Characteristics of the SDA and SCL bus lines for I2C-bus devices
Parameter
Symbol
1 SCL clock frequency
fSCL
2 Bus free time between a STOP and START condition
tBUF
3 Hold time (repeated) START condition. After this period, the first clock tHD;STA
pulse is generated
4 LOW period of the SCL clock
tLOW
5 HIGH period of the SCL clock
tHIGH
6 Set-up time for a repeated START condition
tSU;STA
7 Data hold time:
tHD;DAT
8 Data set-up time
tSU;DAT
9 Set-up time for STOP condition
tSU;STO
All values referred to VIH min. and VIL max. Levels (see Table 2).
Fast-mode I2C-bus
Min. Max.
0 400
1.3
0.6
1.3
0.6
0.6
300*
300*
0.6
Unit
kHz
μS
μS
μS
μS
μS
μS
ns
μS
Table 2. Characteristics of the SDA and SCL I/O stages for I2C-bus devices
Parameter
Symbol
10 LOW level input voltage: fixed input levels
11 HIGH level input voltage: fixed input levels
12 Pulse width of spikes which must be suppressed by the input filter.
13
LOW level output voltage (open drain or open collector): at 3mA sink
current.
14
Input current each I/O pin with an input voltage between 0.4V and 0.9
VDDmax.
VIL
VIH
tSP
VOL1
Ii
Fast-mode devices
Min. Max.
-0.3 1
2.3 5
0 50
0 0.4
-10 10
Unit
V
V
ns
V
μA
SCL clock frequency:250kHz
Figure 13. A command timing example in the I2C data transmission
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
7/30
TSZ02201-0V2V0E100030-1-2
2012.10.05 Rev.001

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부품번호상세설명 및 기능제조사
BD3490FV

Sound Processors

ROHM Semiconductor
ROHM Semiconductor

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