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PA7128 데이터시트 PDF




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부품번호 PA7128 기능
기능 Programmable Electrically Erasable Logic Array
제조업체 Integrated Circuit Technology
로고 Integrated Circuit Technology 로고


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PA7128 데이터시트, 핀배열, 회로
CPoAmInm7due1src2triai8al/l
PA7128 PEELTM Array
Programmable Electrically Erasable Logic Array
Features
s CMOS Electrically Erasable Technology
Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)
Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85 °C temperatures
s Versatile Logic Array Architecture
12 I/Os, 14 inputs, 36 registers/latches
Up to 36 logic cell output functions
PLA structure with true product-term sharing
Logic functions and registers can be I/O-buried
s Ideal for Combinatorial, Synchronous and Asyn-
chronous Logic Applications
Integration of multiple PLDs and random logic
Buried counters, complex state-machines
Comparitors, decoders, other wide-gate functions
s Flexible Logic Cell
Up to 3 output functions per logic cell
D,T and JK registers with special features
Independent or global clocks, resets, presets, clock
polarity and output enables
Sum-of-products logic for output enables
s Development and Programmer Support
ICT PLACE Development Software
Fitters for ABEL, CUPL and other software
Programming support by ICT PDS-3 and other popu-
lar third-party programmers.
s High-Speed Commercial and Industrial Versions
General Description
The PA7128 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7128 offers a versatile
logic array architecture with 12 I/O pins, 14 input pins and
36 registers/latches (12 buried logic cells, 12 input regis-
ters/latches, 12 buried I/O registers/latches). Its logic array
implements 50 sum-of-products logic functions that share
64 product terms. The PA7128’s logic and I/O cells (LCCs,
IOCs) are extremely flexible offering up to three output
functions per cell (a total of 36 for all 12 logic cells). Cells
are configurable as D, T and JK registers with independent
or global clocks, resets, presets, clock polarity and other
special features, making the PA7128 suitable for a variety of
combinatorial, synchronous and asynchronous logic appli-
cations. The PA7128 offers pin compatibility and super-set
functionality to popular 28-pin PLDs, such as the 26V12.
Thus, designs that exceed the architectures of such
devices can be expanded upon. The PA7128 supports
speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (fMAX)
at moderate power consumption 105mA (75mA typical).
Packaging includes 28-pin DIP, SOIC and PLCC (see Fig-
ure 1). Development and programming support for the
PA7128 is provided by ICT and popular third-party develop-
ment tool manufacturers.
2
Figure 1. Pin Configuration
Figure 2. Block Diagram
1/CLK1
I
I
I
I
I
Vcc
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 1/CLK2
27 I/O
26 I/O
25 I/O
24 I/O
23 I/O
22 I/O
21 GND
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
DIP
PLCC
1/CLK
1
1
1
1
1
1
Vcc
1
1
1
1
1
1
1
Global Cells
Input Cells
Logic Control Cells
I/O Cells
1CLK2
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SOIC
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PA7128 pdf, 반도체, 판매, 대치품
PA7128
A.C. Electrical Characteristics Sequential
Symbol
tSCI
tSCX
tCOI
tCOX
tHX
tSK
tAK
tHK
tSI
tHI
tPK
tSPI
tHPI
tSD
tHD
tSDP
tHDP
tCK
tCW
fMAX1
fMAX2
fMAX3
fMAX4
fTGL
tPR
tST
tAW
tRT
tRTV
tRTC
tRW
tRESET
Parameter6,12
Internal set-up to system clock8 - LCC14
(tAL + tSK + tLC - tCK)
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI)
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC)
System-clock to Output Ext. - LCC (tCOI + tLO)
Input hold time from system clock - LCC
LCC Input set-up to async. clock13 - LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC14 (tSK - tCK)
Input hold time from system clock - IOC/INC14 (tSK - tCK)
Array input to IOC PCLK clock
Input set-up to PCLK clock17 - IOC/INC (tSK-tPK-tIA)
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK)
Input set-up to system clock - IOC/INC Sum-D15
(tIA + tAL + tLC + tSK - tCK)
Input hold time from system clock - IOC Sum-D
Input set-up to PCLK clock
(tIA + tAL + tLC + tSK - tPK) - IOC Sum-D
Input hold time from PCLK clock - IOC Sum-D
System-clock delay to LCC/IOCINC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(tSCI + tCOI)
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI)
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX)
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX)
Max. system-clock toggle frequency 1/(tCW + tCW)
LCC presents/reset to LCC output
Input to Global Cell present/reset (tIA + tAL + tPR)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (tRT + tRTV)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state2
-20
Min Max
5
7
7
11
0
2
1
4
0
4
6
0
6
7
0
7
0
6
6
83.3
71.4
62.5
55.5
83.3
1
11
8
7
1
8
10
5
-20 / I-20
Min Max
7
10
9
14
0
2
1
4
0
5
7
0
8
10
0
10
0
7
7
62.5
52.6
47.6
41.6
71.4
2
15
8
9
2
11
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
µs
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부품번호상세설명 및 기능제조사
PA7128

Programmable Electrically Erasable Logic Array

Integrated Circuit Technology
Integrated Circuit Technology

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