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9290X01 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 9290X01
기능 S5L9290X01
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9290X01 데이터시트, 핀배열, 회로
DIGITAL SIGNAL PROCESSOR FOR CDP
PRELIMINARY
S5L9290X
INTRODUCTION
S5L9290X is a signal processing LSI for the CD. Digital processing function
(EFM demodulation, error correction), spindle motor servo processing, wide
capture range DPLL and 1-bit DAC for the CD player are installed in
S5L9290X.
48-LQFP-0707
FEATURES
• Signal processing part
— EFM data demodulation
— Frame sync detection, protection, insertion
— Sub code data processing (Q data CRC check, Q data register installed)
— Error correction (C1: 2 error correction, C2: 4 erasure correction)
— Installed 16K SRAM for De-interleave
— Interpolation
— Digital audio interface
— CLV servo control (X1, X2)
— Wide capture range digital PLL ( ± 50%)
• Digital filter, DAC part
— 4 times over sampling digital filter
— Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz)
— Sigma-delta stereo DAC installed
— Audio L.P.F installed
ORDERING INFORMATION
Device
S5L9290X01L0R0
Package
48-LQFP-0707
Supply Voltage
2.7V 3.3V (Analog, Internal logic)
2.7V 5.5V (I/O port)
Operating Temperature
-20°C +75°C
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9290X01 pdf, 반도체, 판매, 대치품
PRELIMINARY
S5L9290X
PIN DESCRIPTION
DIGITAL SIGNAL PROCESSOR FOR CDP
Table 1. Pin Description
NO. NAME
I/O
Pin Description
1 VSSA_PLL - Analog Ground for DPLL
2 VCO1LF O Pump out for VCO1
3 VSSD_PLL - Digital Ground Separated Bulk Bias for DPLL
4 VDDD_PLL - Digital Power Separated Bulk Bias for DPLL (3V Power)
5 VDDD1-5V - Digital Power (5V Power, I/O PAD)
6 XIN I X'tal oscillator input (16.9344MHz)
7 XOUT O X'tal oscillator output
8 VSSD1 - Digital Ground (I/O PAD)
9 EFMI
I EFM signal input
10 LOCK O CLV Servo locking status output
11 SMEF O LPF time constant control of the spindle servo error signal
12 SMDP O Phase control output for Spindle Motor drive
13 SMDS O Speed control output for Spindle Motor drive
14 WDCK O Word clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz)
15 TESTV
I Various Data/Clock Input
16 LKFS O The Lock status output of frame sync
17 C4M O 4.2336MHz clock output
18 RESETB
I System Reset at 'L'
19 MLT
I Latch signal input from Micom
20 MDAT
I Serial data input from Micom
21 MCK
I Serial data receiving clock input from Micom
22 ISTAT O The internal status output to Micom
23 S0S1 O Subcode sync signal(S0+S1) output
24 SQCK
I Subcode-Q data transfering bit clock input
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9290X01 전자부품, 판매, 대치품
DIGITAL SIGNAL PROCESSOR FOR CDP
AC CHARACTERISTIC
When Pulse is Applied to XIN (Ta = 25°C, VDD = 3.0V, VSS = 0V)
Item
'H' level pulse width
'L' level pulse width
Pulse frequency
Input 'H' level
Input 'L' level
Rising & falling time
Symbol
TWH
TWL
TCK
VIH
VIL
TR,TF
Min
13
13
26
VDD-1.0
-
-
Typ
-
-
-
-
-
-
PRELIMINARY
S5L9290X
Max Unit
- ns
- ns
- ns
-V
0.8 V
10 ns
TCK
TWH
TWL
TR TF
VIH_max
VIH_max*0.9
VDD/2
VIL_max*0.1
VIL_min
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9290X01

S5L9290X01

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