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PDF TSI350 Data sheet ( Hoja de datos )
| Número de pieza | TSI350 | |
| Descripción | PCI-to-PCI Bridge | |
| Fabricantes | Tundra Semiconductor | |
| Logotipo |  |
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Tsi350™
PCI-to-PCI Bridge
Features
PCI Interfaces
• Industry-standard 32-bit, 66-MHz PCI
bridge
• Fully PCI Local Bus Specification,
Revision 2.3 compliant
• Supports up to nine PCI bus masters on
the secondary interface
• Ten independent secondary clock
outputs to the secondary slots
• Primary and secondary interfaces can be
operated using asynchronous clocks
• Secondary clock can either be derived
from the input primary clock or supplied
by an external clock source
• Secondary clocks can be masked
through the GPIO interface during
power up
The Tsi350 makes it possible to extend a
system’s load capability limit beyond that of a
single PCI bus by allowing motherboard
designers to add more PCI devices or more PCI
option card slots than a single PCI bus can
support.
• Supports four independent delayed
transactions in each direction
• Supports up to nine secondary requests
and grants
• External arbiter support on the
secondary bus
• Supports CompactPCI Hot Swap
functionality
• CI Power management with D3Hot
support with option to disable clocks
during D3Hot state
• Supports Bus Locking mechanism
• VGA/Palette memory and I/O decoding
options
• Optional non-posted entry flush upon
posted writes traveling the same
direction
• Compatible with existing solutions from
Intel, TI, PLX, and Pericom
The Tundra Semiconductor Tsi350 is a PCI-to-PCI bridge that is fully
compliant with PCI Local Bus Specification, Revision 2.3. The Tsi350 has
sufficient clock and arbitration pins to support nine PCI bus master devices
directly on its secondary interface.
The Tsi350 allows the two PCI buses to operate concurrently. This means that
a master and a target on the same PCI bus can communicate while the other
PCI bus is busy. This traffic isolation may increase system performance in
applications such as multimedia.
The Tsi350 makes it possible to extend a system’s load capability limit beyond
that of a single PCI bus by allowing motherboard designers to add more PCI
devices or more PCI option card slots than a single PCI bus can support.
The Tsi350 has two identical PCI Interfaces that each handle PCI transactions
for its respective bus, and, depending on the type of transaction, can act as
either a bus master or a bus slave. These interfaces transfer data and control
information flowing to and from the blocks shown below.
Block Diagram
IEEE1149.1
Boundary Scan
JTAG
Clocking/
Reset
Hot
Swap
66 MHz / 32-bit
PCI Bus
Posted
Write
Buffer
Posted
Queue
Non-
Posted
Buffer
Non-
Posted
Queue
Mux
Logic
Mux
Logic
Non-
Posted
Buffer
Non-
Posted
Queue
Posted
Write
Buffer
Posted
Queue
66 MHz / 32-bit
PCI Bus
Address
Decoder
Secondary
Bus Arbiter
80D5000_BK001_02
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