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PDF 82562EP Data sheet ( Hoja de datos )
| Número de pieza | 82562EP | |
| Descripción | 10/100 Mbps Platform LAN Connect | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82562EP 10/100 Mbps Platform LAN www.DataSheet4U.com
Connect (PLC)
Networking Silicon
Datasheet
Product Features
■ IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
■ IEEE 802.3u Auto-Negotiation support
■ Digital Adaptive Equalization control
■ Link status interrupt capability
■ XOR tree mode support
■ 3-port LED support (speed, link and
activity)
■ 10BASE-T auto-polarity correction
■ Alert on LAN functionality
■ Diagnostic loopback mode
■ 1:1 transmit transformer ratio support
■ Low power (less than 300 mW in active
transmit mode)
■ Reduced power in “unplugged mode” (less
than 50 mW)
■ Automatic detection of “unplugged mode”
■ 3.3 V device
■ Lead-free1 64-pin Plastic Ball Grid Array
Package for both leaded and lead-free
designs. (Devices that are lead-free are
marked with a circled “e1” and have the
product code prefix: PCxxxxxx).
1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist
as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead
impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-
banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as
previous versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel
Field Sales representative.
Revision 2.0
September 2005
1 page  
1.0
1.1
1.2
1.3
Introduction
Networking Silicon — 82562EP
www.DataSheet4U.com
Overview
The Intel® 82562EP is a highly-integrated Platform LAN Connect (PLC) device designed for 10 or
100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The
IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5
unshielded twisted pair cable or Type 1 shielded twisted pair cable.
The 82562EP complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full
Duplex Flow Control standard. The 82562EP also includes a PHY interface compliant to the
current PLC interface.
References
• IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers.
• LAN Connect Interface Specification. Intel Corporation.
• I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
Programming information can be obtained through your local Intel representatives.
Product Codes
The product ordering code for a lead-free device is: PC82562EP.
The product ordering code for a leaded device is: RC82562EP.
Datasheet
1
5 Page 
3.6
3.7
Networking Silicon — 82562EP
LED Pins
www.DataSheet4U.com
Pin Name
LILED#
ACTLED#
SPDLED#
Type
O
O
O
Description
Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates
link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either
mode, the LILED# is asserted.
Activity LED. The LED is active low and the Activity LED signal indicates either
receive or transmit activity. When no activity is present, the LED is off. The Activity
LED will flicker when activity is present. The flicker rate depends on the activity load.
The individual address LED control bit in the ICH2 EEPROM (Word Ah, bit 4) can
select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in
Wake on LAN (WOL) mode.
0b = In WOL mode, the ACTLED is activated by the transmission and reception of
broadcast and individual address match packets.
1b = In WOL mode, the ACTLED is activated by the transmission and reception of
individual address match packets only.
This bit is configured by the OEM and is activated by a transmission and reception of
individual address match packets.
Speed LED. The LED is active low and the Speed LED signal indicates the speed of
operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX
operation and off in 10BASE-T mode.
Miscellaneous Control Pins
Pin Name
ADV10
ISOL_TCK
ISOL_TI
ISOL_TEX
TOUT
TESTEN
Type
Description
I Advertise 10 Mbps Only. The this signal is asserted high, the 82562EP
advertises only 10BASE-T technology during Auto-Negotiation processes in this
state. Otherwise, the 82562EP advertises all of its technologies.
Note: ADV10 has an internal pull-down resistor.
I Test Clock. The Test Clock signal sets the device into asynchronous test mode
in conjunction with the Test Input, Test Execute and Test Enable pins (refer to
Table 1).
In the manufacturing test mode, it acts as the test clock.
Note: ISOL_TCK has an internal pull-down resistor.
I Test Input. The Test Input signal sets the device into asynchronous test mode in
conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table
1).
In the manufacturing test mode, it acts as the test data input pin.
Note: ISOL_TI has an internal pull-down resistor.
I Test Execute. The Test Execute signal sets the device into asynchronous test
mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to
Table 1).
In the manufacturing test mode, it places the command that was entered through
the ISOL_TI pin in the instruction register.
Note: ISOL_TEX has an internal pull-down resistor.
O Test Output. The Test Output pin is used for Boundary XOR scan output. In the
manufacturing test mode, it acts as the test output port.
I Test Enable. The Test Enable pin is used to enable test mode and should be tied
to the pull-down resistor for normal operation.
Datasheet
7
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 82562EP.PDF ] | |
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