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부품번호 SC18IS602B 기능
기능 I2C-bus to SPI bridge
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SC18IS602B 데이터시트, 핀배열, 회로
SC18IS602/602B/603
I2C-bus to SPI bridge
Rev. 04 — 11 March 2008
Product data sheet
1. General description
www.DataSheet4U.com
The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a
standard I2C-bus of a microcontroller and an SPI bus. This allows the microcontroller to
communicate directly with SPI devices through its I2C-bus. The SC18IS602/602B/603
operates as an I2C-bus slave-transmitter or slave-receiver and an SPI master. The
SC18IS602/602B/603 controls all the SPI bus-specific sequences, protocol, and timing.
The SC18IS602/602B has its own internal oscillator, while the SC18IS603 requires an
external clock source for operation. SC18IS602 and SC18IS603 do not support SS2
function as SPI slave select signal; this pin can only be used as GPIO2.
2. Features
I I2C-bus slave interface operating up to 400 kHz
I SPI master operating up to 1.8 Mbit/s (SC18IS602/602B) or 4 Mbit/s (SC18IS603)
I 200-byte data buffer
I Up to four slave select outputs
I Up to four programmable I/O pins
I Operating supply voltage: 2.4 V to 3.6 V
I Low power mode
I Internal oscillator option
I Active LOW interrupt output
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA
I Very small 16-pin TSSOP
3. Applications
I Converting I2C-bus to SPI
I Adding additional SPI bus controllers to an existing system




SC18IS602B pdf, 반도체, 판매, 대치품
NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
7. Functional description
The SC18IS602/602B/603 acts as a bridge between an I2C-bus and an SwPwI win.tDeraftaacSeh.eeItt4U.com
allows an I2C-bus master device to communicate with any SPI-enabled device.
7.1 I2C-bus interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes
A typical I2C-bus configuration is shown in Figure 4. (Refer to NXP Semiconductors’
UM10204, “I2C-bus specification and user manual”, document order number
9398 393 40011.)
I2C-bus
VDD
RPU
RPU
SDA
SCL
SC18IS602/602B/603
I2C-BUS
DEVICE
I2C-BUS
DEVICE
002aac445
Fig 4. I2C-bus configuration
The SC18IS602/602B/603 device provides a byte-oriented I2C-bus interface that supports
data transfers up to 400 kHz. When the I2C-bus master is reading data from SC18IS60x,
the device will be a slave-transmitter. The SC18IS60x will be a slave-receiver when the
I2C-bus master is sending data. At no time does the SC18IS60x act as an I2C-bus master,
however, it does have the ability to hold the SCL line LOW between bytes to complete its
internal processes.
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
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SC18IS602B 전자부품, 판매, 대치품
NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
7.1.5 Configure SPI Interface - Function ID F0h
The SPI hardware operating mode, data direction, and frequency can bewchwawn.gDeadtabSyheet4U.com
sending a ‘Configure SPI Interface’ command to the I2C-bus.
SC18IS602_602B_603_4
Product data sheet
S SLAVE ADDRESS W A F0h A DATA A P
002aac450
Fig 10. Configure SPI Interface
After the SC18IS602/602B/603 address is transmitted on the bus, the Configure SPI
Interface Function ID (F0h) is sent followed by a byte which will define the SPI
communications.
The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing
data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 20 and
Figure 21 show the different settings of Clock Phase bit CPHA.
Table 4.
Bit
Symbol
Reset
Configure SPI Interface (F0h) bit allocation
76543
X X ORDER X MODE1
XX0X0
2
MODE0
0
1
F1
0
0
F0
0
Table 5.
Bit
7:6
5
4
3:2
1:0
Configure SPI Interface (F0h) bit description
Symbol
Description
- reserved
ORDER
When logic 0, the MSB of the data word is transmitted first.
If logic 1, the LSB of the data word is transmitted first.
- reserved
MODE1:MODE0 Mode selection
00 - SPICLK LOW when idle; data clocked in on leading edge
(CPOL = 0, CPHA = 0)
01 - SPICLK LOW when idle; data clocked in on trailing edge
(CPOL = 0, CPHA = 1)
10 - SPICLK HIGH when idle; data clocked in on trailing edge
(CPOL = 1, CPHA = 0)
11 - SPICLK HIGH when idle; data clocked in on leading edge
(CPOL = 1, CPHA = 1)
F1:F0
SPI clock rate
SC18IS602/602B:
00 - 1843 kHz
01 - 461 kHz
10 - 115 kHz
11 - 58 kHz
SC18IS603:
00 - fosc4
01 - fosc16
10 - fosc64
11 - fosc128
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
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