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P3P623S09B 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 P3P623S09B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 P3P623S09B 자료 제공

부품번호 P3P623S09B 기능
기능 Timing-Safe Peak EMI Reduction IC
제조업체 ON Semiconductor
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P3P623S09B 데이터시트, 핀배열, 회로
P3P623S05A/B and P3P623S09A/B
Timing-Safe™ Peak EMI
Reduction IC
General Features
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Input frequency range: 20MHz - 50MHz
Multiple low skew Timing-safe™ Outputs:
P3P623S05: 5 Outputs
P3P623S09: 9 Outputs
Supply Voltage: 3.3V±0.3V
Packaging Information:
P3P623S05: 8 pin TSSOP
P3P623S09:16 pin TSSOP
True Drop-in Solution for Zero Delay Buffer
Functional Description
P3P623S05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute Timing-Safe™ clocks with Peak
EMI reduction. P3P623S05 is an eight-pin version,
accepts one reference input and drives out five low-skew
Timing-Safe™ clocks. P3P623S09 accepts one reference
input and drives out nine low-skew Timing-Safe™ clocks.
All parts have on-chip PLLs that lock to an input clock on
General Block Diagram
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple P3P623S05 / P3P623S09 devices can accept
the same input clock and distribute it. In this case, the
skew between the outputs of the two devices is
guaranteed to be less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to
be less than ±350pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Refer Spread Spectrum Control and Input-Output Skew
Table” for deviations and Input-Output Skew for
P3P623S05A/B and P3P623S09A/B devices.
P3P623S05/09 operates from a 3.3V supply and is
available in TSSOP package, as shown in the ordering
information table.
Application
P3P623S05/09 is targeted for use in Displays and
memory interface systems.
CLKIN
PLL
P3P623S05A/B
www.DataSheet4U.com
CLKOUT
CLK1
CLK2
CLK3
CLKIN
PLL
MUX
CLK4
S2
Select Input
Decoding
S1
P3P623S09A/B
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
©2010 SCILLC. All rights reserved.
July 2010 – Rev. 1
Publication Order Number:
P3P623S05/D




P3P623S09B pdf, 반도체, 판매, 대치품
Pin Configuration for P3P623S09A/B
P3P623S05A/B and
P3P623S09A/B
CLKIN 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
P3P623S09A/B
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Pin Description for P3P623S09A/B
Pin #
1
2
3
Pin Name
CLKIN1
CLKA12
CLKA22
Pin Type
Description
I External reference Clock input, 5V tolerant input
O Buffered clock Bank A output4
O Buffered clock Bank A output4
4 VDD
P 3.3V supply
5 GND
6 CLKB12
7 CLKB22
S23
8
S13
9
10 CLKB32
11 CLKB42
P Ground
O Buffered clock Bank B output4
O Buffered clock Bank B output4
I Select input, bit 2.
See Select Input Decoding table for P3P623S09A/B for more details
I Select input, bit 1.
See Select Input Decoding table for P3P623S09A/B for more details
O Buffered clock Bank B output4
O Buffered clock Bank B output4
12 GND
P Ground
13 VDD
P 3.3V supply
14 CLKA32
www.DataSheet4U.com
15 CLKA42
O Buffered clock Bank A output4
O Buffered clock Bank A output4
16
Notes:
CLKOUT2
O Buffered clock output.Internal feedback on this pin.
1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
Rev. 1 | Page 4 of 11 | www.onsemi.com

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P3P623S09B 전자부품, 판매, 대치품
Switching Waveforms
Duty Cycle Timing
OUTPUT
VDD/2
t1
t2
VDD/2
P3P623S05A/B and
P3P623S09A/B
VDD/2
All Outputs Rise/Fall Time
OUTPUT
2V
0.8V
t3
2V
0.8V
t4
Output - Output Skew
OUTPUT
OUTPUT
VDD/2
VDD/2
t5
Input - Output Propagation Delay
www.DataSheet4U.com
INPUT
OUTPUT
VDD/2
VDD/2
t6
Rev. 1 | Page 7 of 11 | www.onsemi.com

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