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PDF PJDLLLC70 Data sheet ( Hoja de datos )
| Número de pieza | PJDLLLC70 | |
| Descripción | Very Low Capacitance Diode Array | |
| Fabricantes | Pan Jit International | |
| Logotipo |  |
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PJDLLLC70
Very Low Capacitance Diode Array
This diode array is configured to protect up to two high speed data
transmission lines, used in Low Voltage Differential Signal (LVDS) ports.
Acting as a line terminator, minimizes overshoot and undershoot conditions
due to bus impedance as well as protect against over-voltage events as
electrostatic discharges. The line-line concept minimizes the problems to
customers to re-route PCB lines, simplifying the design.
SPECIFICATION FEATURES
Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground
Maximum Leakage Current of 1µA @ VRWM
Industry Standard SMT Package SOT563
IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact*
100% Tin Matte finish (LEAD-FREE PRODUCT)
APPLICATIONS
USB 2.0 and Firewire Port Protection
HDMI Version 1.3
DVI
MARKING : 70
SOT563 Package
1
2
3
6
5
4
Line1 +VREF Line2
654
1 23
Line1 Gnd Line2
Note: pins 1and 6 (Line1) as well as pins 3
and 4 (Line2) must be connected
externally, as the drawing attached below.
I/O Line 1 1
6
GND
2
5 +VREF
I/O Line 2 3
4
Line-line concept ease the PCB design, directly placing the device over
the data lines, opening only the contact points. VREF is fixed by the
operating voltage, referenced to the ground.
MAXIMUM RATINGS Tj = 25°C Unless otherwise noted
Rating
Peak Pulse Current (8/20µs Waveform)
Rectifier Repetitive Peak Reverse Voltage
www.DataSOhpeeetr4aUti.ncogmJunction Temperature Range
Storage Temperature Range
Soldering Temperature, t max = 10s
Symbol
IPPM
VRRM
TJ
Tstg
TL
Value
12
70
-55 to +125
-55 to +150
260
Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected.
Units
A
V
°C
°C
°C
7/23/2009
Page 1
www.panjit.com
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| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet PJDLLLC70.PDF ] | |
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