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64F3039 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 64F3039
기능 HD64F3039
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64F3039 데이터시트, 핀배열, 회로
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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64F3039 pdf, 반도체, 판매, 대치품
Preface
The H8/3039 Series comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3039 Series to adapt quickly and flexibly to a variety of conditions.
In addition to its masked-ROM versions, the H8/3039 Series has an F-ZTATTM* version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3039 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
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64F3039 전자부품, 판매, 대치품
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 86
5.2.3 IRQ Status Register (ISR) .................................................................................... 91
5.2.4 IRQ Enable Register (IER) .................................................................................. 92
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 93
5.3 Interrupt Sources................................................................................................................ 94
5.3.1 External Interrupts................................................................................................ 94
5.3.2 Internal Interrupts ................................................................................................. 95
5.3.3 Interrupt Vector Table .......................................................................................... 95
5.4 Interrupt Operation ............................................................................................................ 98
5.4.1 Interrupt Handling Process ................................................................................... 98
5.4.2 Interrupt Sequence................................................................................................ 103
5.4.3 Interrupt Response Time ...................................................................................... 104
5.5 Usage Notes ....................................................................................................................... 105
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 105
5.5.2 Instructions that Inhibit Interrupts........................................................................ 106
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 106
5.5.4 Usage Notes.......................................................................................................... 106
Section 6 Bus Controller ................................................................................................ 109
6.1 Overview............................................................................................................................ 109
6.1.1 Features ................................................................................................................ 109
6.1.2 Block Diagram...................................................................................................... 110
6.1.3 Input/Output Pins.................................................................................................. 111
6.1.4 Register Configuration ......................................................................................... 111
6.2 Register Descriptions......................................................................................................... 112
6.2.1 Access State Control Register (ASTCR).............................................................. 112
6.2.2 Wait Control Register (WCR).............................................................................. 113
6.2.3 Wait State Controller Enable Register (WCER) .................................................. 114
6.2.4 Address Control Register (ADRCR).................................................................... 115
6.3 Operation ........................................................................................................................... 117
6.3.1 Area Division........................................................................................................ 117
6.3.2 Bus Control Signal Timing .................................................................................. 119
6.3.3 Wait Modes .......................................................................................................... 121
6.3.4 Interconnections with Memory (Example)........................................................... 127
w6w.4w.DUatsaaSgheeNeto4tUes.c.o..m.................................................................................................................... 129
6.4.1 Register Write Timing.......................................................................................... 129
6.4.2 Precautions on setting ASTCR and ABWCR* .................................................... 129
Section 7 I/O Ports ........................................................................................................... 131
7.1 Overview............................................................................................................................ 131
7.2 Port 1.................................................................................................................................. 135
7.2.1 Overview .............................................................................................................. 135
7.2.2 Register Descriptions............................................................................................ 135
iii

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64F3039

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