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PDF MAX5556 Data sheet ( Hoja de datos )
| Número de pieza | MAX5556 | |
| Descripción | Low-Cost Stereo Audio DAC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0550; Rev 1; 2/11
Low-Cost Stereo Audio DAC
General Description
The MAX5556 stereo audio sigma-delta digital-to-analog
converter (DAC) offers a simple and complete stereo
digital-to-analog solution for media servers, set-top
boxes, video-game hardware, automotive rear-seat
entertainment, and other general consumer audio appli-
cations. This DAC features built-in digital interpolation/fil-
tering, sigma-delta digital-to-analog conversion, and
analog output filtering. Control logic and mute circuitry
minimize audible pops and clicks during power-up,
power-down, clock changes, or when invalid clock con-
ditions occur.
The MAX5556 receives input data over a 3-wire
I2S-compatible interface with left-justified audio data.
Data can be clocked by either an external or internal
serial clock. The internal serial clock frequency is pro-
grammable by selection of a master clock (MCLK) and
sample clock (LRCLK) ratio. Sampling rates from 2kHz
to 50kHz are supported.
The MAX5556 operates from a single +4.75V to +5.5V
analog supply with total harmonic distortion plus noise
below -87dB. This device is available in an 8-pin SO
package and is specified over the -40°C to +85°C
industrial temperature range.
Applications
Digital Video Recorders and Media Servers
Set-Top Boxes
Video-Game Hardware
Automotive Rear-Seat Entertainment
Features
o Simple and Complete Stereo Audio DAC
Solutions, No Controls to Set
o Sigma-Delta Stereo DACs with Built-In
Interpolation and Analog Output Filters
o I2S-Compatible Digital Audio Interface
o Clickless/Popless Operation
o 3.5VP-P Output Voltage Swing
o -87dB THD+N
o +87dB Dynamic Range
o Sample Frequencies (fS) from 2kHz to 50kHz
o Master Clock (MCLK) up to 25MHz
o Automatic Detection of Clock Ratio (MCLK/
LRCLK)
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
DATA FORMAT
MAX5556ESA+
-40°C to
+85°C
8 SO
Left-justified I2S
data
MAX5556ESA/V+
-40°C to
+85°C
8 SO
Left-justified I2S
data
+Denotes a lead(Pb)-free/RoHS-compliant package. For lead-
ed version, contact factory.
/V denotes an automotive-qualified part.
Typical Operating Circuit
+5V
Pin Configuration
VDD
AUDIO
DECOMPRESSION
SDATA
SCLK
LRCLK
SERIAL
INTERFACE
www.DataSheet4U.com
OUTL
DAC
MAX5556
CLOCK
MCLK
DAC
GND
OUTR
FILTER
FILTER
LEFT
OUTPUT
LINE-LEVEL
BUFFER
RIGHT
OUTPUT
LINE-LEVEL
BUFFER
TOP VIEW
+
SDATA 1
SCLK 2
LRCLK 3
MAX5556
MCLK 4
8 OUTL
7 VDD
6 GND
5 OUTR
SO
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Low-Cost Stereo Audio DAC
Typical Operating Characteristics
(VDD = +5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.)
STOPBAND REJECTION
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FREQUENCY (NORMALIZED TO fS)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.40
TRANSITION BAND
0.44 0.48 0.52 0.56
FREQUENCY (NORMALIZED TO fS)
0.60
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.40
TRANSITION BAND DETAIL
0.42 0.44 0.46 0.48 0.50
FREQUENCY (NORMALIZED TO fS)
0.52
0.25
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
0
PASSBAND RIPPLE
0.1 0.2 0.3 0.4
FREQUENCY (NORMALIZED TO fS)
0.5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0
0dBFS FFT
16,000-SAMPLE FFT USING 1kHz INPUT
2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0
-60dBFS FFT
16,000-SAMPLE FFT USING 1kHz INPUT
2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)
IDLE-CHANNEL NOISE FFT
0
-10
-20
-30
-40
-50
-60 16,000-SAMPLE FFT WITH NO INPUT
-70
-80
-90
-100
www.Data-S11h0eet4U.com
-120
-130
-140
0 2 4 6 8 10 12 14 16 18
FREQUENCY (kHz)
20
TWIN-TONE IMD FFT
0
-10
-20
-30
-40
-50
-60 16,000-SAMPLE FFT
-70 WITH 13kHz AND
-80 14kHz INPUT SIGNALS
-90
-100
-110
-120
-130
-140
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)
THD+N vs. AMPLITUDE
-60
-70
-80 UNWEIGHTED
-90
INPUT = 1kHz 18-BIT SIGNAL
-100 A-WEIGHTED
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
-110
-60 -50 -40 -30 -20 -10 0
AMPLITUDE (dBFS)
_______________________________________________________________________________________ 5
5 Page 
Low-Cost Stereo Audio DAC
Left/Right Clock Input (LRCLK)
LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (fS). On the
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). The
MAX5556 accepts data at LRCLK audio sample rates
from 2kHz to 50kHz.
Master Clock (MCLK)
MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock fre-
quencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies list-
ed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.
The MAX5556 detects the MCLK/LRCLK ratio during
the initialization sequence by counting the number of
MCLK transitions during a single LRCLK period. MCLK,
SCLK, and LRCLK must be synchronous signals.
Table 1. Internal and External Clock
Frequencies
INTERNAL SERIAL
CLOCK FREQUENCY
MCLK/LRCLK
= 256 OR 512
MCLK/LRCLK
= 384
32 x fS
48 x fS
EXTERNAL SERIAL
CLOCK FREQUENCY
User defined
(Figure 4)
Table 2. MCLK/LRCLK Ratios
LRCLK
(kHz)
32
44.1
48
MCLK/LRCLK
= 256
8.1920
11.2896
12.2880
MCLK (MHz)
MCLK/LRCLK
= 384
12.2880
16.9344
18.4320
MCLK/LRCLK
= 512
16.3840
22.5792
24.5760
Data Formats
MAX5556 I2S Left-Justified Data Format
The MAX5556 accepts data with an I2S left-justified
data format, accepting 16 or 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.
The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x fS) in internal serial
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x fS).
External Analog Filter
Use an external lowpass analog filter to further reduce
harmonic images, noise, and spurs. The external analog
filter can be either active or passive depending upon
performance and design requirements. For example fil-
ters, see Figures 8 and 9 and the Applications
Information section. Careful attention should be paid
when selecting capacitors for audio signal path applica-
tions. NPO and C0G types are recommended as are alu-
minum electrolytics and low-ESR tantalum varieties. Use
of generic ceramic types is not recommended and may
result in degraded THD performance. Always consult
manufacturers’ data sheets and applications information.
OUTL
MAX5556
100kΩ
R = 560Ω
C = 1.5nF
www.DataSheet4U.com
OUTR
100kΩ
R = 560Ω
C = 1.5nF
Figure 8. Passive Component Analog Output Filter
______________________________________________________________________________________ 11
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MAX5556.PDF ] | |
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