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부품번호 | CY14E101I 기능 |
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기능 | 1-Mbit (128 K X 8) Serial (I2C) nvSRAM | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
CY14C101I
PRELIMINARY
CY14B101I, CY14E101I
1 Mbit (128K x 8) Serial (I2C) nvSRAM
with Real Time Clock
Features
■ 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K x 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using
I2C
command (Software STORE) or HSB pin (Hardware STORE)
❐
RorEbCyAIL2CL
to SRAM initiated on power-up (Power
command (Software RECALL)
Up
RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 250 uA
❐ Sleep mode current of 8 uA
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ Real Time Clock (RTC)
❐ Full-featured RTC
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 uA (typical)
■ High-speed I2C interface
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast mode Plus: 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for 1/4, 1/2, or entire array
■ Industry standard configurations
❐ Operating voltages:
• CY14C101I: VCC = 2.4 V to 2.6 V
• CY14B101I: VCC = 2.7 V to 3.6 V
• CY14E101I: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101I/CY14B101I/CY14E101I combines a
1-Mbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 128 K words of 8 bits each. The embedded nonvol-
atile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL opera-
tions can also be initiated by the user through I2C commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Serial Number
8x8
Manufacture ID/
Product ID
Power Control
Block
Sleep
Memory Control Register
Command Register
Quantrum Trap
128 K x 8
SDA
SCL
A2, A1
WP
www.DataSheet4U.com
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
SRAM
128 K x 8
STORE
RECALL
X in
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-54391 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 21, 2011
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
I2C Interface
I2C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) – that carry information between multiple devices
on the bus. I2C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to Vcc using resistors. The choice of a pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock, and all the data
I/Os are transmitted in synchronization with this clock. The
CY14X101I supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a 7-bit slave address that the
master intends to communicate with and R/W bit indicating a
read or a write operation. The selected slave responds to this
with an acknowledgement (ACK). After a slave is selected, the
remaining part of the communication takes place between the
master and the selected slave device. The other devices on the
bus ignore the signals on the SDA line until a STOP or Repeated
START condition is detected. The data transfer is done between
the master and the selected slave device through the SDA pin
synchronized with the SCL clock generated by the master.
I2C Protocol – Data Transfer
Each transaction in I2C protocol starts with the master
generating a START condition on the bus, followed by a 7-bit
slave address and eighth bit (R/W) indicating a read (1) or a write
(0) operation. All signals are transmitted on the open-drain SDA
line and are synchronized with the clock on SCL line. Each byte
of data transmitted on the I2C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after the
receive/transmit of each byte on the falling edge of the ninth
clock cycle. The new address is latched just prior to
sending/receiving the acknowledgment bit. This allows the next
sequential byte to be accessed with no additional addressing. On
reaching the last memory location, the address rolls back to
0x00000 and writes continue. The slave responds to each byte
sent by the master during a write operation with an ACK. A write
sequence can be terminated by the master generating a STOP
or Repeated START condition.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The NACK
signal causes the CY14X101I to release the SDA line and the
master can then generate a STOP or a Repeated START
condition to initiate a new operation.
www.DataSheet4U.com
Document #: 001-54391 Rev. *C
Page 4 of 42
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4페이지 PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
High-Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device in high-speed mode. This enables master/slave
communication for speeds up to 3.4 MHz. A stop condition will
exit Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Single and multiple-byte reads and writes are supported. After
the device enters Hs-mode, data transfer continues in Hs-mode
until stop condition is sent by master device. The slave switches
back to F/S-mode after a STOP condition (P). To continue data
transfer in Hs-mode, the master sends Repeated START (Sr).
See Figure 13 on page 12 and Figure 16 on page 13 for
HS-mode timings for read and write operation.
Figure 6. Data Transfer Format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
S MASTER CODE A Sr SLAVE ADD. R/W A
DATA
A/A P
n (bytes+ack.)
Hs-mode continues
Sr SLAVE ADD.
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X101I
reserves three sets of upper 4 MSBs [7:4] in the slave device
address field for accessing the Memory, RTC Registers, and
Table 2. Slave Device Addressing
Control Registers. The accessing mechanism is described in the
following section.
The nvSRAM product provides three different functionalities:
Memory, RTC Registers and Control Registers functions (such
as serial number and product ID). The three functions of the
device are accessed through different slave device addresses.
The first four most significant bits [7:4] in the device address
register are used to select between the nvSRAM functions.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
nvSRAM
Function Select
CY14X101I Slave Devices
1 0 1 0 Device select ID A16 R/W Selects Memory
Memory, 128K x 8
1
1
0
1
Device select ID
X
R/W
Selects RTC
Registers
RTC Registers, 16 x 8
www.D0ataShee0t4U.com1
1
Device select ID
X
R/W
Selects Control
Registers
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
- Command Register, 1 × 8
Document #: 001-54391 Rev. *C
Page 7 of 42
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CY14E101I | 1 Mbit (128K x 8) Serial (I2C) nvSRAM | Cypress Semiconductor |
CY14E101I | 1-Mbit (128 K X 8) Serial (I2C) nvSRAM | Cypress Semiconductor |
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