PDF MK2049-45 Data sheet ( Hoja de datos )

Número de pieza	MK2049-45
Descripción	3.3V Communications Clock PLL
Fabricantes	Integrated Circuit Systems
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No Preview Available ! MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal for filtering jitter from high frequency clocks. In External Mode, ICLK accepts an 8 kHz clock and will produce output frequencies from a table of common communciations clock rates, CLK and CLK/2. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-45 can be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. ICS can customize these devices for many other different frequencies. Contact your ICS representative for more details. Features • Packaged in 20 pin SOIC • 3.3 V + 5% operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to 8 kHz + 100 ppm (External mode) • Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs • Exact internal ratios enable zero ppm error • Output rates include T1, E1, T3, E3, and OC3 submultiples • Available in Pb (lead) free package • See also the MK2049-34 and MK2049-36 Block Diagram RSET ISET CP CS RS CAP2 CL CAP1 X1 CL Optional Crystal Load Caps External Pullable Crystal X2 ICLK Reference Divider (used in buffer mode only) Phase Detector VCXO PLL VCXO Charge Pump Feedback Divider (N) www.DFaSt3a:0Sh4eet4UL.Docioovikmd-eurpVTaalbulee Reference Divider VCO Translator PLL Feedback Divider Output Divider Divide by 2 CLK CLK/2 8k MDS 2049-45 G 1 Revision 101904 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 1 page MK2049-45 3.3V Communications Clock PLL Charge Pump Current Table RSET (kΩ) 13.02 15 16 18 20 22 24 27 36 47 56 75 100 150 200 Charge Pump Current (ICP) (µA) 139 125 119 109 100 93 86 68 56 43 35 28 22 15 12 Special considerations must be made in choosing loop components CS and CP. These recommendations can be found at http://www.icst.com/products/telecom/loopfiltercap.htm Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. (The optional series termination resistor is not shown in the External Component Schematic.) Decoupling Capacitors As with any high performance mixed-signal IC, the MK2049-45 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2049-45 should use one common connection to www.DthaetaSPhCeeBt4pUo.wcoemr plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. Recommended Power Supply Connection for Optimal Device Performance Connection to 3.3V Power Plane Ferrite Bead Bulk Decoupling Capacitor (such as 1 µF Tantalum) VDD Pin VDD Pin VDD Pin 0.01 µF Decoupling Capacitors Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Please refer to MAN05 for the procedure to determine capacitor values. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01 µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system MDS 2049-45 G 5 Revision 101904 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 5 Page

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