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PDF SH7211 Data sheet ( Hoja de datos )
| Número de pieza | SH7211 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0344-0200
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
32
SH7211 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family
SH7211
R5F72115D160FPV
www.DataSheet4U.com
Rev.2.00
Revision Date: May. 8, 2008
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
• Product Type, Package Dimensions, etc.
10. Main Revisions and Additions in this Edition (only for revised versions)
www.DataSheet4U.com
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00 May. 08, 2008 Page v of xxiv
REJ09B0344-0200
5 Page 
5.5.1 Interrupt Sources..................................................................................................... 90
5.5.2 Interrupt Priority Level ........................................................................................... 91
5.5.3 Interrupt Exception Handling.................................................................................. 92
5.6 Exceptions Triggered by Instructions .................................................................................. 93
5.6.1 Types of Exceptions Triggered by Instructions ...................................................... 93
5.6.2 Trap Instructions ..................................................................................................... 94
5.6.3 Slot Illegal Instructions ........................................................................................... 94
5.6.4 General Illegal Instructions..................................................................................... 95
5.6.5 Integer Division Instructions................................................................................... 95
5.7 When Exception Sources Are Not Accepted ....................................................................... 96
5.8 Stack Status after Exception Handling Ends........................................................................ 97
5.9 Usage Notes ......................................................................................................................... 99
5.9.1 Value of Stack Pointer (SP) .................................................................................... 99
5.9.2 Value of Vector Base Register (VBR) .................................................................... 99
5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ........... 99
Section 6 Interrupt Controller (INTC) .................................................................101
6.1 Features.............................................................................................................................. 101
6.2 Input/Output Pins ............................................................................................................... 103
6.3 Register Descriptions ......................................................................................................... 104
6.3.1 Interrupt Priority Registers 01, 02, 05 to 15 (IPR01, IPR02, IPR05 to IPR15) .... 105
6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 107
6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 108
6.3.4 IRQ Interrupt Request Register (IRQRR)............................................................. 109
6.3.5 Bank Control Register (IBCR).............................................................................. 111
6.3.6 Bank Number Register (IBNR)............................................................................. 112
6.4 Interrupt Sources................................................................................................................ 114
6.4.1 NMI Interrupt........................................................................................................ 114
6.4.2 User Break Interrupt ............................................................................................. 114
6.4.3 H-UDI Interrupt .................................................................................................... 114
6.4.4 IRQ Interrupts ....................................................................................................... 115
6.4.5 On-Chip Peripheral Module Interrupts ................................................................. 116
w6w.5w.DIanttaeSrrhuepett4EUx.cceopmtion Handling Vector Table and Priority ................................................... 117
6.6 Operation ........................................................................................................................... 125
6.6.1 Interrupt Operation Sequence ............................................................................... 125
6.6.2 Stack after Interrupt Exception Handling ............................................................. 128
6.7 Interrupt Response Time.................................................................................................... 129
6.8 Register Banks ................................................................................................................... 135
6.8.1 Banked Register and Input/Output of Banks ........................................................ 136
6.8.2 Bank Save and Restore Operations....................................................................... 136
Rev. 2.00 May. 08, 2008 Page xi of xxiv
REJ09B0344-0200
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