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ADP323 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP323은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADP323 기능
기능 (ADP322 / ADP323) High PSRR Voltage Regulator
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ADP323 데이터시트, 핀배열, 회로
FEATURES
Fixed (ADP322) and adjustable output (ADP323) options
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
Three 200 mA low dropout voltage regulators (LDOs)
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 µF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Overcurrent and thermal protection
Key specifications
High PSRR
76 dB PSRR up to 1 kHz
70 dB PSRR at 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
Low output noise
29 µV rms typical output noise at VOUT = 1.2 V
55 µV rms typical output noise at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV at 200 mA load
85 µA typical ground current at no load, all LDOs enabled
100 µs fast turn-on circuit
Guaranteed 200 mA output current per regulator
−40°C to +125°C junction temperature
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP322/ADP323 200 mA triple output LDOs combine high
PSRR, low noise, low quiescent current, and low dropout voltage
to extend the battery life of portable devices and are ideally
suited for wireless applications with demanding performance
and board space requirements.
The ADP322/ADP323 PSRR is greater than 60 dB for frequencies
www.DasahtaigShheaest140U0.ckoHmz while operating with a low headroom voltage.
The ADP322/ADP323 offer much lower noise performance
than competing LDOs without the need for a noise bypass
capacitor.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
ADP322/ADP323
TYPICAL APPLICATION CIRCUITS
2.5V TO VBIAS
5.5V
+
1µF
ADP322 VBIAS
1.8V TO VIN1/VIN2
5.5V
+
1µF ON
EN1
OFF
LDO 1
EN LD1
VBIAS
VOUT1
+
1µF
1.8V TO VIN3
5.5V
ON
EN2
OFF
+
1µF ON
EN3
OFF
LDO 2
EN LD2
VBIAS
LDO 3
EN LD3
VOUT2
+
1µF
VOUT3
+
1µF
GND
Figure 1. Typical Application Circuit for ADP322
2.5V TO VBIAS
5.5V
+
1µF
ADP323 VBIAS
1.8V TO VIN1/VIN2
5.5V
+
1µF ON
EN1
OFF
LDO 1
EN LD1
VBIAS
1.8V TO VIN3
5.5V
ON
EN2
OFF
+
1µF ON
EN3
OFF
LDO 2
EN LD2
VBIAS
LDO 3
EN LD3
VOUT1
FB1
+
1µF
VOUT2
FB2
+
1µF
VOUT3
FB3
+
1µF
GND
Figure 2. Typical Application Circuit for ADP323
The ADP322/ADP323 are available in a miniature 16-lead,
3 mm × 3 mm LFCSP package and are stable with tiny 1 µF
±30% ceramic output capacitors providing the smallest possible
board area for a wide variety of portable power needs.
The ADP322 is available in output voltage combinations ranging
from 0.8 V to 3.3 V and offers overcurrent and thermal protection
to prevent damage in adverse conditions. The APDP323
adjustable triple LDO can be configured for any output voltage
between 0.5 V and 5 V with two resistors for each output.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.




ADP323 pdf, 반도체, 판매, 대치품
ADP322/ADP323
Parameter
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
UNDERVOLTAGE LOCKOUT
Input Bias Voltage (VBIAS)
Rising
Input Bias Voltage (VBIAS)
Falling
Hysteresis
OUTPUT NOISE
Symbol
VIH
VIL
VI-LEAKAGE
UVLO
UVLORISE
UVLOFALL
UVLOHYS
OUTNOISE
POWER SUPPLY REJECTION RATIO PSRR
Conditions
2.5 V ≤ VBIAS ≤ 5.5 V
2.5 V ≤ VBIAS ≤ 5.5 V
EN1 = EN2 = EN3 = VIN or GND
EN1 = EN2 = EN3 = VIN or GND,
TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V
VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
VIN = 3.8 V, VOUT = 2.8 V, IOUT = 100 mA
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
Min Typ Max Unit
1.2 V
0.4 V
0.1 µA
1 µA
2.45 V
2.0 V
180 mV
63 µV rms
55 µV rms
50 µV rms
29 µV rms
70 dB
70 dB
70 dB
60 dB
40 dB
68 dB
62 dB
68 dB
60 dB
40 dB
1 Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on
the tolerances of the resistors used.
2 Based on an end-point calculation using 1 mA and 200 mA loads.
3 The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input-to-output voltage differential when the
input voltage is set to the nominal output voltage.
4 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE1
CAPACITOR ESR
Symbol
CMIN
RESR
Conditions
TA = −40°C to +125°C
TA = −40°C to +125°C
Min Typ Max Unit
0.70 µF
0.001
1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with LDOs.
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Rev. 0 | Page 4 of 24

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ADP323 전자부품, 판매, 대치품
ADP322/ADP323
EN1 1
VBIAS 2
VIN1/VIN2 3
FB1 4
ADP323
12 GND
11 NC
10 VIN3
9 FB3
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GROUND PLANE.
Figure 4. ADP323 Pin Configuration
Table 6. ADP323 Pin Function Descriptions
Pin No. Mnemonic Description
1 EN1
Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For
automatic startup, connect EN1 to VBIAS.
2
VBIAS
Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 µF or greater capacitor.
3 VIN1/VIN2 Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 µF or
greater capacitor.
4 FB1
Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1.
5
VOUT1
Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND.
6
VOUT2
Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND.
7 FB2
Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2.
8
VOUT3
Regulated Output Voltage 3. Connect a 1 µF or greater output capacitor between VOUT3 and GND.
9 FB3
Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3.
10 VIN3
Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 µF or greater capacitor.
11 NC
Not connected internally.
12 GND
Ground Pin.
13 NC
Not connected internally.
14 NC
Not connected internally.
15 EN3
Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For
automatic startup, connect EN3 to VBIAS.
16 EN2
Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For
automatic startup, connect EN2 to VBIAS.
EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.
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