Datasheet.kr   

78Q21x3-DB 데이터시트 PDF




Teridian Semiconductor에서 제조한 전자 부품 78Q21x3-DB은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 78Q21x3-DB 자료 제공

부품번호 78Q21x3-DB 기능
기능 MII Evaluation Board
제조업체 Teridian Semiconductor
로고 Teridian Semiconductor 로고


78Q21x3-DB 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 15 페이지수

미리보기를 사용할 수 없습니다

78Q21x3-DB 데이터시트, 핀배열, 회로
78Q21x3-DB MicroPHYTM
MII Evaluation Board
DEMO BOARD MANUAL
April 2007
DESCRIPTION
The 78Q21x3-DB is a design example for a
10/100BASE-TX Mbit/second Fast Ethernet MII
Interface adaptor. A 78Q2123 or 78Q2133
MicroPHY transceiver from Teridian provides the
network physical interface and MII (Medium
Independent Interface) interface.
Teridian Semiconductor’s MicroPHY is an auto-
sensing, auto-switching 10/100BASE-TX Fast
Ethernet transceiver with full duplex operation
capability. The device interfaces directly to the
IEEE-802.3u MII port.
Full-featured MII
management functions are included along with an
extended register set. The MicroPHY five bit PHY
address is defaulted to 0x001. The MicroPHY
interfaces to CAT5 UTP cable via a 1:1 transformer.
The transceiver’s transmitter includes on-chip the
pulse shaper and low power line driver. The
receiver incorporates a sophisticated combination of
real-time adaptive equalization, an adaptive DC
offset adjustment circuit and baseline wander
correction. Smart squelch circuitry further improves
the receiver’s noise rejection. Full featured auto-
negotiation or parallel detect modes are supported.
The demo board requires operation with a +3.3V
power supply.
Design Kit contains:
MicroPHY MII Demo Board
www.DataSheeDt4eUm.coomBoard Parts List
P.C.B. Gerber Files
Demo Board schematic
MicroPHY Data Sheet
10/100Base-TX Interface
RJ45 Pin Assignment
Pin Signal
Pin Signal
1 TX+
5 N/C
2 TX-
6 RX-
3 RX+
7 N/C
4 N/C
8 N/C
MII: Medium Independent Interface
Pin Assignment:
(40 Pin Male Subminiature D, 0.050)
Pin Signal
Pin Signal
1 +3.3V
21 +3.3V
2 MDIO
22 COMMON
3 MDC
23 COMMON
4 RXD3
24 COMMON
5 RXD2
25 COMMON
6 RXD1
26 COMMON
7 RXD0
27 COMMON
8 RXDV
28 COMMON
9 RXCLK
29 COMMON
10 RXER
30 COMMON
11 TXER
31 COMMON
12 TXCLK
32 COMMON
13 TXEN
33 COMMON
14 TXD0
34 COMMON
15 TXD1
35 COMMON
16 TXD2
36 COMMON
17 TXD3
37 COMMON
18 COL
38 COMMON
19 CRS
39 COMMON
20 +3.3V
40 +3.3V
Ordering Number
78Q21x3-DB
Description
MicroPHY MII Demo Board
© 2007 Teridian Semiconductor Corporation, Proprietary and Confidential
-1-
Rev_2.3




78Q21x3-DB pdf, 반도체, 판매, 대치품
78Q21x3-DB MicroPHYTM
MII Evaluation Board
DEMO BOARD MANUAL
fd
The following devices integrate the transformers, RJ45 connector, LEDs, and termination resistors.
Commercial Temperature Connectors
Vendor
Pulse
Part number
J0011D21
J0011D21NL
J0011D21B
J0011D21BNL
J0011D21E
J0011D21ENL
J0011D01
J0011D01NL
J0011D01B
J0011D01BNL
J0012D21
J0012D21NL
J1011F01P
J1011F01PNL
J1011F21P
J1011F21PNL
Tab up
/down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
Up
Up
Up
LED
No
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
LED color
(L/R)
N/A
N/A
G/Y
G/Y
G/G
G/G
N/A
N/A
G/Y
G/Y
N/A
N/A
G/Y
G/Y
G/Y
G/Y
Shielding
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Lead-
free
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Compatible
Footprints *
a
a
b
b
b
b
a
a
b
b
a
a
A
A
A
A
Halo
HFJ11-2450EURL
Down
HFJ11-2450EU-L11RL Down
HFJ11-2450ERL
Down
HFJ11-2450E-L11RL Down
HFJT1-S003E-L11RL Up
HFJT1-S003-L11RL Up
HFJT1-S003
Up
No
Yes
No
Yes
Yes
Yes
No
N/A No
G/G No
N/A Yes
G/G Yes
G/G Yes
G/G Yes
N/A Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
e
f
c
d
B
C
D
www.DataSheet4U.com
© 2007 Teridian Semiconductor Corporation, Proprietary and Confidential
-4-
Rev_2.3

4페이지










78Q21x3-DB 전자부품, 판매, 대치품
PCB Layout Considerations
78Q21x3-DB MicroPHYTM
MII Evaluation Board
DEMO BOARD MANUAL
fd
The following recommendations enhance the MicroPHY’s performance while minimizing EMC emissions:
1. The transformer to transceiver signal traces must be 100differential transmission lines.
2. Place the termination network components near the input data pins of the transceiver or transformer.
3. Make all differential signal pairs short and of the same length.
4. Decouple the transceiver thoroughly with 0.01µF and 0.1µF capacitors.
5. Locate these decoupling capacitors as close as possible to the respective transceiver VCC and GND
pins.
6. All decoupling capacitor and transceiver VCC and GND connections should tie immediately to a VCC or
GND plane via with minimum trace inductance.
7. Total decoupling capacitance should be greater than the load capacitance that the digital output drivers
must drive.
8. Use low inductance, ceramic surface mount decoupling capacitors.
9. Use a multi-layer PCB with the inner layers dedicated to GND and VCC.
10. A single VCC and GND plane is recommended for optimum performance. The lowest possible series
impedance is required between the analog and digital VCC and GND pins respectively of the transceiver.
11. The outer layers of a 4 layer PCB are to be used for signal routing.
12. Place the highest speed signals on the layer adjacent to the GND plane.
13. Physically separate the analog signals from the digital signals by placing them on opposite layers or
routing them away from each other.
14. Additional component and solder side ground layers may be added for maximum EMC containment.
15. The GND plane should extend out to the transceiver side of the transformer. Remove the VCC and GND
planes from the line side of the transformer to the RJ-45 connector.
16. Do not allow the chassis ground plane to cross over the transceiver GND plane. Minimum separation
must accommodate over 1.5kV.
17. Provide onboard termination of the unused signal pairs in the CAT-5 cable.
18. Use a shielded RJ-45 connector with its case stakes soldered to the chassis ground.
19. Locate the transformer adjacent to the RJ-45 to minimize the shunt capacitance to the line.
20. Minimize RF current fringing by making the VCC plane 0.10 inch smaller than the GND plane. If multiple
transceivers are used, provide partitions in the VCC and GND planes between the analog sections.
Maintain the partition from the transformer up to the transceiver’s analog interface. Do not cross these
partitions with signal traces, in particular any digital signals from adjacent transceivers.
21. Add series resistors on all transceiver MII outputs to minimize digital output driver peak currents.
22. Minimize the use of vias when routing the analog signal traces.
23. Isolate the crystal and its capacitors from the analog signals with a guard ring.
24. The crystal compensation capacitor value (C2 & C3) must be selected to trim the oscillator’s frequency to
25.0000 MHz ± 50ppm. The optimum value will be layout dependent. A mere ±4pF can shift the 25MHz
± 100Hz. The 25.0000 MHz ±50ppm is specified by the IEEE.
Note: System vendors need to select the proper crystal according to their applications, such as operating
environment, product lifetime, and etc since crystal aging, operating temperature, and other factors can
affect the crystal frequency tolerance.
www.DataSheet4U.com
© 2007 Teridian Semiconductor Corporation, Proprietary and Confidential
-7-
Rev_2.3

7페이지


구       성 총 15 페이지수
다운로드[ 78Q21x3-DB.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
78Q21x3-DB

MII Evaluation Board

Teridian Semiconductor
Teridian Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵