PDF MSC8126 Data sheet ( Hoja de datos )

Número de pieza	MSC8126
Descripción	Quad Digital Signal Processor
Fabricantes	Freescale Semiconductor
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Freescale Semiconductor Data Sheet: Document Number: MSC8126 Rev. 14, 5/2008 MSC8126 Quad Digital Signal Processor FC PBGA–431 20 mm × 20 mm • Four StarCore™ SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes. • 475 Kbyte M2 memory for critical data/temporary data buffering. • 4 Kbyte boot ROM. • M2-accessible multi-core MQBus connecting the M2 memory with all four cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic control of M2 memory access by the cores and local bus. • Internal PLL configured are reset by configuration signal values. • 60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices. • Direct slave interface (DSI) using a 32/64-bit slave interface with 21–25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal/external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support. • Three mode signal multiplexing: 64-bit DSI/32-bit system bus, 32-bit DSI/64-bit system bus, or 32-bit DSI/32-bit system bus. • Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64-/32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for www.DatIaPSBhuesepte4rUip.hcoermals and internal memories. • Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • Ethernet controller: support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII). • UART with full-duplex operation up to 6.25 Mbps. • Up to 32 general-purpose input/output (GPIO) ports. • I2C interface that allows booting from EEPROM devices. • Two timer modules, each with sixteen configurable 16-bit timers. • Eight programmable hardware semaphores. • Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; thirty-two virtual maskable interrupts (8 per core) and four virtual NMI (one per core) that can be generated by a simple write access. • Boot options: external memory, external host, UART, TDM, or I2C. • VCOP with fully programmable feed-forward channel decoding, feed-forward channel equalization and traceback sessions. Up to 400 3GPP 12.2 kbps AMR channels (channel decoding, number of channels linear to frequency). Up to 200 blind transport format detect (BTFD) channels according to the 3GPP standard. Number of channels linear to frequency. • TCOP with full support for 3GPP and CDMA2000 standards in Turbo decode; up to 20 turbo-coding 384 kbps channels; 8 state PCCC with polynomial as supported by the 3G standards; iterative decoding structure based on Maximum A-Posteriori probability (MAP), with calculations performed in the LOG domain. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. 1 page Pin Assignments Top View 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 B VDD GND GND NMI_ OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0 VDD VDD GND C GND VDD TDO S RESET GPIO28 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6 D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8 E TCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO12 F PO RESET RST CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_ CLK ETHTX_ CLK GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19 G HA24 HA27 HA25 HA23 HA17 PWE0 VDD VDD BADDR 31 BM0 ABB VDD INT_ ETHCR OUT S VDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO22 H HA20 HA28 VDD HA19 TEST PSD CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31 J HA18 HA26 VDD HA13 GND PSDA BADDR MUX 27 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30 K HA15 HA21 HA16 PWE3 PWE1 POE BADDR 30 Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28 L HA12 HA14 HA11 VDDH VDDH BADDR BADDR 28 29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 M HD28 HD31 VDDH GND GND VDDH VDD VDDH GND GND VDDH HB RST VDDH VDDH GND VDDH A24 A21 N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS 0 HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20 P HD20 HD27 HD25 HD23 HWBS 3 HWBS 2 HWBS 1 HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSD VAL DP0 VDDH GND A19 R HD18 VDDH GND HD22 HWBS HWBS 64 TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16 T HD17 HD21 HD1 HD0 HWBS HWBS 75 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14 U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13 V HD3 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6 Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5 AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3 AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD www.DataSheet4U.com Figure 3. MSC8126 Package, Top View Freescale Semiconductor MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 14 5 5 Page Des. T15 T16 T17 T18 T19 T20 T21 T22 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 W15 W16 W17 W18 W19 W20 W21 www.DaWta2S2heet4U.com Y2 Y3 Y4 Y5 Pin Assignments Table 1. MSC8126 Signal Listing by Ball Designator (continued) Signal Name D23 IRQ5/DP5/DACK4/EXT_BG3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ1/DP1/DACK1/EXT_BG2 D30 GND A15 A14 HD16 HD19 HD2/DSI64 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH VDDH HD33/D33/reserved VDDH HD32/D32/reserved GND GND A7 A6 HD7 HD15 VDDH HD9 Des. V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 Signal Name D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 HD6 HD5/CNFGS HD4/MODCK2 GND GND VDDH VDDH GND HDST1/HA10 HDST0/HA9 VDDH GND HD40/D40/ETHRXD0 VDDH HD54/D54/ETHTX_EN HD52/D52 VDDH GND VDDH HD46/D46/ETHTXT0 GND HD42/D42/ETHRXD2/reserved HD38/D38/reserved HD35/D35/reserved A0 Freescale Semiconductor MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 14 11 11 Page

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