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PDF CY62147DV18 Data sheet ( Hoja de datos )
| Número de pieza | CY62147DV18 | |
| Descripción | 4-Mb (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62147DV18
MoBL2™
4-Mb (256K x 16) Static RAM
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
Functional Description[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
Logic Block Diagram
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
DATA IN DRIVERS
AA190
A8
A7
A6
A5 256K x 16
A4 RAM Array
A3
A2
AA01
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
www.DataSheet4U.com
Power -Down
Circuit
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05343 Rev. *B
Revised February 26, 2004
1 page  
CY62147DV18
MoBL2™
Datawqewqewq Retention Waveform[9]
VCC
CE or
BHE.BLE
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
Switching Characteristics Over the Operating Range [10.]
55 ns
70 ns
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC Read Cycle Time
55
70 ns
tAA Address to Data Valid
55 70 ns
tOHA
Data Hold from Address Change
10
10 ns
tACE CE LOW to Data Valid
55 70 ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to LOW Z[11]
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11]
CE HIGH to High Z[11, 12]
25 35 ns
5 5 ns
16 16 ns
10 10 ns
20 25 ns
tPU
CE LOW to Power-Up
0
0 ns
tPD CE HIGH to Power-Down
55 70 ns
tDBE
BLE / BHE LOW to Data Valid
55
70 ns
tLZBE
BLE / BHE LOW to Low Z[11]
10
10 ns
tHZBE
BLE / BHE HIGH to HIGH Z[11, 12]
20
25 ns
Write Cycle[13]
tWC Write Cycle Time
55
70 ns
tSCE
CE LOW to Write End
40
50 ns
tAW
Address Set-up to Write End
40
50 ns
tHA
Address Hold from Write End
0
0 ns
tSA
Address Set-up to Write Start
0
0 ns
tPWE
WE Pulse Width
40
45 ns
tBW
BLE / BHE LOW to Write End
40
50 ns
tSD
Data Set-Up to Write End
25
30 ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High-Z[11, 12]
WE HIGH to Low-Z[11]
0 0 ns
20 25 ns
10 10 ns
Notes:
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10.
11.
Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference
pulse levels
At any given
otef m0 ptoerVaCtuCr(etypa.n),davnodltoaugtepucot nlodaitdioinng,
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levels
is less
of VCC(typ)/2, input
than tLZWE for any
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high impedence state.
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be ACTIVE
the edge of
to initiate
the signal
a write and any
that terminates
the write.
Document #: 38-05343 Rev. *B
Page 5 of 11
5 Page 
CY62147DV18
MoBL2™
Document History Page
Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM
Document Number: 38-05343
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
127482 06/17/03
HRT New Data Sheet
*A
131009 11/26/03
CBD Changed From Advance to Preliminary
*B
229908 See ECN
AJU Changed From Preliminary to Final
Added 70 ns speed bin
Changed Vcc MAX spec from 2.20V to 2.25V
Modified VIH spec on footnote #6 from VCC (MAX) + 0.5V to VCC (MAX) + 0.75V
Changed ICC TYP values from 8 mA to 6 mA
Changed ICC MAX values at Vcc (max) = 1.95V from 15 mA to 12 mA (L bin)
and 10 mA to 8mA (LL bin)
Changed ICC MAX values at Vcc (max) = 2.25V from 18 mA to 15 mA (L bin)
and 12mA to 10 mA (LL bin)
With modified Vcc MAX spec, changed ISB1 and ISB2 MAX values from 15 uA
to 18 uA (L bin) and 10 uA to 12 uA (LL bin)
Modified input and output capacitance values
Removed footnote #9 from earlier rev
Removed MAX value for VDR
Modified tHZOE from 20 ns to 16 ns
Added Pb-free ordering information
www.DataSheet4U.com
Document #: 38-05343 Rev. *B
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY62147DV18.PDF ] | |
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