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K6R4004C1C-E 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K6R4004C1C-E은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 K6R4004C1C-E 기능
기능 1Mx4 Bit High Speed Static RAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K6R4004C1C-E 데이터시트, 핀배열, 회로
PRELIMINARY
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E CMOS SRAM
Document Title
1Mx4 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
Rev. 2.0
History
Initial release with Preliminary.
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics
1.3 Changed ISB1 to 20mA
2.1 Relax D.C parameters.
Item
12ns
ICC 15ns
20ns
Previous
160mA
155mA
150mA
Current
190mA
185mA
180mA
Draft Data
Feb. 12. 1999
Mar. 29. 1999
Remark
Preliminary
Preliminary
Aug. 19. 1999 Preliminary
Rev. 3.0
2.2 Relax Absolute Maximum Rating.
Item
Voltage on Any Pin Relative to Vss
Previous
-0.5 to 7.0
Current
-0.5 to Vcc+0.5
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
10ns
12ns
15ns
20ns
ICC
-
190mA
185mA
180mA
Previous
Isb
70mA
Isb1
20mA
ICC
160mA
150mA
140mA
130mA
Current
Isb
60mA
Isb1
10mA
Mar. 27. 2000 Final
3.3 Added Extended temperature range
www.DataSheet4U.com
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 3.0
March 2000




K6R4004C1C-E pdf, 반도체, 판매, 대치품
PRELIMINARY
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
3ns
1.5V
See below
* The above test conditions are also applied at extended and industrial temperature range.
Output Loads(A)
DOUT
ZO = 50
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
RL = 50
VL = 1.5V
30pF*
DOUT
255
+5.0V
480
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Symbol
K6R4004C1C-10
Min Max
K6R4004C1C-12
Min Max
Read Cycle Time
tRC 10 - 12 -
Address Access Time
tAA - 10 - 12
Chip Select to Output
tCO - 10 - 12
Output Enable to Valid Output
Chip Enable to Low-Z Output
tOE - 5 - 6
tLZ 3 - 3 -
Output Enable to Low-Z Output
tOLZ
0
-
0
-
Chip Disable to High-Z Output
tHZ 0 5 0 6
Output Disable to High-Z Output
tOHZ
0
5
0
6
Output Hold from Address Change
tOH
3
-
3
-
Chip Selection to Power Up Time
tPU
0
-
0
-
Chip Selection to Power DownTime tPD
- 10 - 12
www.Data*SThheeeat4bUov.ecpoamrameters are also guaranteed at extended and industrial temperature range.
K6R4004C1C-15
Min Max
15 -
- 15
- 15
-7
3-
0-
07
07
3-
0-
- 15
K6R4004C1C-20
Min Max
20 -
- 20
- 20
-8
3-
0-
09
09
3-
0-
- 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-4-
Rev 3.0
March 2000

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K6R4004C1C-E 전자부품, 판매, 대치품
PRELIMINARY
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E CMOS SRAM
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS WE
HX
LH
LH
LL
* X means Dont Care.
OE
X*
H
L
X
Mode
Not Select
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
DOUT
DIN
Supply Current
ISB, ISB1
ICC
ICC
ICC
www.DataSheet4U.com
-7-
Rev 3.0
March 2000

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관련 데이터시트

부품번호상세설명 및 기능제조사
K6R4004C1C-C

1Mx4 Bit High Speed Static RAM

Samsung semiconductor
Samsung semiconductor
K6R4004C1C-E

1Mx4 Bit High Speed Static RAM

Samsung semiconductor
Samsung semiconductor

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