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K7I163684B 데이터시트 PDF




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부품번호 K7I163684B 기능
기능 512Kx36 & 1Mx18 DDRII CIO b4 SRAM
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K7I163684B 데이터시트, 핀배열, 회로
K7I163684B
K7I161884B
512Kx36 & 1Mx18 DDRII CIO b4 SRAM
18Mb DDRII SRAM Specification
165FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
www.DataSheet4U.com
- 1 - Rev. 5.0 July 2006




K7I163684B pdf, 반도체, 판매, 대치품
K7I163684B
K7I161884B
512Kx36 & 1Mx18 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I163684B(512Kx36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ NC/SA* NC/SA* R/W
BW2
K
BW1
LD
SA NC/SA* CQ
B NC DQ27 DQ18 SA BW3
K
BW0
SA
NC
NC DQ8
C
NC
NC DQ28 VSS
SA
SA0
SA1
VSS
NC
DQ17
DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ2
M NC
NC DQ34 VSS VSS VSS VSS VSS
NC
DQ11
DQ1
N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10
P NC
NC DQ26 SA
SA
C
SA
SA
NC
DQ9
DQ0
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 36Mb, 10A for 72Mb, 2A for 144Mb.
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0,SA1
SA
DQ0-35
R/W
LD
BW0, BW1,BW2, BW3
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
www.DataSheet4U.com
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
10R
11R
2R
1R
2A,10A,3A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
NOTE
1
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin, active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
2
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 4 - Rev. 5.0 July 2006

4페이지










K7I163684B 전자부품, 판매, 대치품
K7I163684B
K7I161884B
512Kx36 & 1Mx18 DDRII CIO b4 SRAM
WRITE OPERATIONS
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 4-bit burst DDR operation, it will write two 36-bit, 18-bit or 8-bit data words with each write command.
The first “late writed” data is transferred and registered in to the device synchronous with next K clock rising edge.
Next burst data is transferred and registered synchronous with following K clock rising edge.
Continuous write operations are initiated with K rising edge.
And “late writed” data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I163684B and K7I161884B will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I163684B and K7I161884B support byte write operations.
With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented.
In K7I161884B BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7I163684B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250resistor will give an output impedance of 50.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
CLOCK CONSIDERATION
K7I163684B and K7I161884B utilize internal DLL (Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
SINGLE CLOCK MODE
K7I163684B and K7I161884B can be operated with the single clock pair K and K,
instead of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device cant change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
DEPTH EXPANSION
www.DaEtfoaarScehhaepceohtr4tbUcaan.cnko.bme selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal
Before chip deselected, all read and write pending operations are completed.
- 7 - Rev. 5.0 July 2006

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K7I163684B

512Kx36 & 1Mx18 DDRII CIO b4 SRAM

Samsung semiconductor
Samsung semiconductor

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